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ZXCW6100S28 数据表(PDF) 18 Page - Zetex Semiconductors |
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ZXCW6100S28 数据表(HTML) 18 Page - Zetex Semiconductors |
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18 / 21 page  DC Dither A function is provided to help eliminate small signal digital zero point switching distortion by the addition of a small DC voltage. This is intended to move the signal away from the DAC zero to prevent the distortion that is sometimes discernible when the DAC switches around zero. DC Dither would be required when using the recommended HPWM mode. If using RPWM DC dither would not normally be set, however, the requirement is application dependant and full details on use are available in the associated Application document. Contact your nearest Zetex office for full details. Bit 36: 0 = DC dither off, 1 = DC dither on Digital interface select Bits 44 and 45 select the digital interface standard required as below: 00 24 bit I 2S 01 Left justify 24 or 32 bit 10 Right justify 16 bit 11 Right justify 24 bit NOVALOAD™ NOVALOAD™ is selected using bits 34 and 35 as below: Bit 34: 0 = NOVALOAD™ off, 1 = NOVALOAD™ on Bit 35: 0 = remove bass control if bass clips, 1 = adjust volume control if bass clips NOVALOAD™ limiter attack rate The limiter attack rate is governed by bits 36 to 39. The code chosen sets the number of word clock periods to reduce the gain by 0.5dB. The number of word clock periods quadruples per digital increment. Code sequence follow: 000 = 1 word clock period per 0.5dB 001 = 4 word clock periods per 0.5dB 010 = 16 word clock periods per 0.5dB 011 = 64 word clock periods per 0.5dB 100 = 256 word clock periods per 0.5dB 101 = 1024 word clock periods per 0.5dB 110 = 4096 word clock periods per 0.5dB 111 = 16384 word clock periods per 0.5dB The default condition is 0010 which is 4 word clock periods. NOVALOAD™ limiter release rate The limiter release rate is governed by bits 40 to 43. The code chosen sets the number of word clock periods to reduce the gain by 0.5dB. The number of word clock periods doubles per digital increment Code examples in the sequence follow: 0000 = 16 word clock periods per 0.5dB 0001 = 32 word clock periods per 0.5dB 0010 = 64 word clock periods per 0.5dB 1110 = 262144 word clock periods per 0.5dB 1111 = 524288 word clock periods per 0.5dB The default condition is 1010 which is 16384 word clock periods. ATAPI The ATAPI CD-ROM standard for mixing and muting is supported by bits 46 to 49. The following logic table defines how the left and right channels are affected by the codes set on these bits: The default setting is 1001 which is left channel = L, right channel = R ZXCW6100S28 ISSUE 1 - JULY 2002 18 ATI3 ATI2 ATI1 ATI0 L channel R channel 0000 MUTE MUTE 0001 MUTE R 0010 MUTE L 0011 MUTE {(L+R)/2} 0100R MUTE 0101R R 0110R L 0111R {(L+R)/2} 1000L MUTE 1001L R 1010L L 1011L {(L+R)/2} 1100 {(L+R)/2} MUTE 1101 {(L+R)/2} R 1110 {(L+R)/2} L 1111 {(L+R)/2} {(L+R)/2} |
类似零件编号 - ZXCW6100S28 |
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类似说明 - ZXCW6100S28 |
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