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SN74ALVTH16501DGV 数据表(PDF) 10 Page - Texas Instruments |
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SN74ALVTH16501DGV 数据表(HTML) 10 Page - Texas Instruments |
10 / 11 page SN54ALVTH16501, SN74ALVTH16501 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCES071D – JUNE 1996 – REVISED JANUARY 1999 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V VOH VOL th tsu From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 Open GND 500 Ω 500 Ω tPLH tPHL Output Control Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 3 V 0 V VOH VOL 0 V VOL + 0.3 V VOH – 0.3 V ≈ 0 V 3 V 0 V 0 V tw Input 3 V 3 V 3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Timing Input Data Input Output Input tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6 V GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. 6 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 0 V 3 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V Figure 2. Load Circuit and Voltage Waveforms |
类似零件编号 - SN74ALVTH16501DGV |
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类似说明 - SN74ALVTH16501DGV |
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