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GS8170LW72C-200 数据表(PDF) 4 Page - GSI Technology |
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GS8170LW72C-200 数据表(HTML) 4 Page - GSI Technology |
4 / 27 page GS8170LW36/72C-333/300/250/200 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.03 1/2005 4/27 © 2002, GSI Technology, Inc. Operation Control All address, data and control inputs (with the exception of EP2, EP3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to rising clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQ2. Pin Description Table Symbol Description Type Comments A Address Input — ADV Advance Input Active High Bx Byte Write Enable Input Active Low W Write Enable Input Active Low E1 Chip Enable Input Active Low E2 & E3 Chip Enable Input Programmable Active High or Low EP2 & EP3 Chip Enable Program Pin Mode Input To be tied directly to VDD, VDDQ or VSS CK Clock Input Active High CQ, CQ Echo Clock Output Three State - Deselect via E2 or E3 False DQ Data I/O Input/Output Three State MCH Must Connect High Input Active High To be tied directly to VDD or VDDQ MCL Must Connect Low Input Active Low To be tied directly to VSS ZQ Output Impedance Control Mode Input Low = Low Impedance [High Drive] High = High Impedance [Low Drive] To be tied directly to VDDQ or VSS TCK Test Clock Input Active High TDI Test Data In Input — TDO Test Data Out Output — TMS Test Mode Select Input — NC No Connect — Not connected to die or any other pin VDD Core Power Supply Input 1.8 V Nominal VDDQ Output Driver Power Supply Input 1.8 V Nominal VSS Ground Input — |
类似零件编号 - GS8170LW72C-200 |
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类似说明 - GS8170LW72C-200 |
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