GS8170LW36/72C-333/300/250/200

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 2.03 1/2005

10/27

© 2002, GSI Technology, Inc.

Echo Clock Control in Two Banks of SigmaRAMs

It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of

Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the

Echo Clocks.

In some applications it may be appropriate to pause between banks; to deselect both RAMs with E1 before resuming read

operations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle

in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2

would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.

Pipelined Read Bank Switch with E1 Deselect

CMOS Output Driver Impedance Control

Read A

Read B

Read C

Read D

Read E

A

B

C

D

E

Q(A)

Q(C)

Q(D)

Q(B)

Q(C)

CK

Address

ADV

E1

E2 Bank1 E2 Bank1

W

CQ Bank1

DQ_Bank1

CQ1+CQ2

CQ Bank2

DQ_Bank2

Read A

Read B

Deselect

Read D

Read E

A

B

D

E

Q(A)

Q(E)

Q(B)

Q(D)

CK

Address

ADV

E1

E2 Bank1 E2 Bank1

W

CQ_Bank1

DQ_Bank1

CQ1+CQ2

CQ_Bank2

DQ_Bank2