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ICE40LP1K-CB81 数据表(PDF) 15 Page - Lattice Semiconductor |
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ICE40LP1K-CB81 数据表(HTML) 15 Page - Lattice Semiconductor |
15 / 52 page iCE40 LP/HX Family Data Sheet © 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02029-3.5 15 I/O Bank 0 I/O Bank 2 PIO OUT OE VCCIO I/O Bank 0, 1, 2, or 3 Voltage Supply = Statically defined by configuration program 0 = Hi-Z 1 = Output Enabled PAD HD iCEGATE HOLD OUTCLK OUTCLK INCLK Enabled 1 Latch inhibits switching for lowest power IN VCCIO_0 VCCIO_2 VCC Internal Core VCC_SPI General-Purpose I/O General-Purpose I/O Programmable Input/Output SPI Bank P ull-up Enable P ull-up GBIN pins optionally connect directly to an associated GBUF global buffer IN Disabled 0 Figure 3.5. I/O Bank and Programmable I/O Cell The PIO contains three blocks: an input register block, output register block iCEgate™ and tri-state register block. To save power, the optional iCEgate latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of modes along with the necessary clock and selection logic. Input Register Block The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed interface signals before they are passed to the device core. In Generic DDR mode, two registers are used to sample the data on the positive and negative edges of the system clock signal, creating two data streams. Output Register Block The output register block can optionally register signals from the core of the device before they are passed to the sysI/O buffers. In Generic DDR mode, two registers are used to capture the data on the positive and negative edge of the system clock and then muxed creating one data stream. Figure 3.6 shows the input/output register block for the PIOs. |
类似零件编号 - ICE40LP1K-CB81 |
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类似说明 - ICE40LP1K-CB81 |
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