iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

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4.19.2. Register-to-Register Performance – HX Devices

Table 4.21. Register-to-Register Performance – HX Devices

Function

Timing

Units

Basic Functions

16:1 MUX

305

MHz

16-bit adder

220

MHz

16-bit counter

255

MHz

64-bit counter

105

MHz

Embedded Memory Functions

256 x 16 Pseudo-Dual Port RAM

403

MHz

Notes:



The above timing numbers are generated using the iCECube2 design tool. Exact performance may vary with device and tool

version. The tool uses internal parameters that have been characterized but are not tested on every device.



4.20. Derating Logic Timing

Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case numbers in

the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing numbers at a

particular temperature and voltage.

4.21. Maximum sysI/O Buffer Performance

I/O Standard

Max. Speed

Units

Inputs

400

MHz

400

MHz

LVCMOS33

250

MHz

LVCMOS25

250

MHz

LVCMOS18

250

MHz

Outputs

LVDS25E

250

MHz

subLVDS18E

155

MHz

LVCMOS33

250

MHz

LVCMOS25

250

MHz

LVCMOS18

155

MHz

Notes:

1.

Measured with a toggling pattern.

2.

Supported in Bank 3 only.