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PE310G4BPI9 数据表(PDF) 3 Page - Silicom Ltd. |
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PE310G4BPI9 数据表(HTML) 3 Page - Silicom Ltd. |
3 / 10 page Silicom Ltd. Connectivity Solutions Page 3 Performance Features: IPV4 and IPV6 Supports for IP/ TCP and IP/UDP Receive Checksum offload Fragmented UDP checksum offload for Packet Reassembly CPU utilization- the 82599 supports reduction in CPU utilization, mainly by supporting Receive Side Coalescing (RSC) Support for 16 virtual machine Device Queues (VMDq) per port Support Direct Cache Access (DCA) Advanced memory architecture reduces latency by preceding TSO packets. A TSO packet may be interleaved with other packets going to the wire Minimized number of device I/O interrupts using MSI and MSI-X Offload of TCP / IP / UDP checksum calculation and TCP segmentation Large on chip receive packet buffer (512 KB) Large on chip transmit packet buffer (160KB) Jumbo Frame (up to 16KB) Host Interface: PCI Express X8 lanes Support PCI Express Base Specification 3.0 (8GT/s) Technical Specifications Bypass Specifications WDT Interval (Software Programmable): 3,276,800 mSec (3,276.8 Sec): Maximum 100 mSec ( 0.1 Sec) : Minimum WDT Interval = (2^wdt_interval_parameter)*(0.1) sec. wdt_interval_parameter: { Valid Range: 0-15} Fiber 10 Gigabit Ethernet Technical Specifications – (10GBASE-SR) Adapters: IEEE Standard / Network topology: Fiber Gigabit Ethernet, 1000Base-SX (850nM) Data Transfer Rate: 10.3125GBd Cables and Operating distance: Up to: Multimode fiber: 62.5um, 160MHz/Km 13m* 62.5um, (OM1)200MHz/Km 16.5m * * Defined as half as the distance as specified in the optical transceiver |
类似零件编号 - PE310G4BPI9 |
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类似说明 - PE310G4BPI9 |
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