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TC59LM814CFT-50 数据表(PDF) 8 Page - Toshiba Semiconductor |
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TC59LM814CFT-50 数据表(HTML) 8 Page - Toshiba Semiconductor |
8 / 38 page TC59LM814/06CFT-50,-55,-60 2002-08-19 8/38 AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued) -50 -55 -60 SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX UNIT NOTES tQSLZ DQS-out Low Impedance Time from CLK −0.65 −0.75 −0.85 3,6,8 tQSHZ DQS-out High Impedance Time from CLK −0.65 0.65 −0.75 0.75 −0.85 0.85 3,7,8 tQPDH Last output to PD High Hold Time 0 0 0 tPDEX Power Down Exit Time 2 2 2 3 tT Input Transition Time 0.1 1 0.1 1 0.1 1 tFPDL PD Low Input Window for Self-Refresh Entry −0.5 × tCK 5 −0.5 × tCK 5 −0.5 × tCK 5 ns 3 tREFI Auto-Refresh Average Interval 0.4 7.8 0.4 7.8 0.4 7.8 5 tPAUSE Pause Time after Power-up 200 200 200 µs CL = 3 5 5 5 IRC Random Read/Write Cycle Time (applicable to same bank) CL = 4 5 5 5 IRCD RDA/WRA to LAL Command Input Delay (applicable to same bank) 1 1 1 1 1 1 CL = 3 4 4 4 IRAS LAL to RDA/WRA Command Input Delay (applicable to same bank) CL = 4 4 4 4 IRBD Random Bank Access Delay (applicable to other bank) 2 2 2 BL = 2 2 2 2 IRWD LAL following RDA to WRA Delay (applicable to other bank) BL = 4 3 3 3 IWRD LAL following WRA to RDA Delay (applicable to other bank) 1 1 1 CL = 3 5 5 5 IRSC Mode Register Set Cycle Time CL = 4 5 5 5 IPD PD Low to Inactive State of Input Buffer 1 1 1 IPDA PD High to Active State of Input Buffer 1 1 1 CL = 3 15 15 15 IPDV Power down mode valid from REF command CL = 4 18 18 18 CL = 3 15 15 15 IREFC Auto-Refresh Cycle Time CL = 4 18 18 18 ICKD REF Command to Clock Input Disable at Self-Refresh Entry 16 16 16 ILOCK DLL Lock-on Time (applicable to RDA command) 200 200 200 cycle |
类似零件编号 - TC59LM814CFT-50 |
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类似说明 - TC59LM814CFT-50 |
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