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CY7C1378B 数据表(PDF) 3 Page - Cypress Semiconductor

部件名 CY7C1378B
功能描述  9-Mbit (256K x 32) Pipelined SRAM with NoBL Architecture
Download  14 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1378B 数据表(HTML) 3 Page - Cypress Semiconductor

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CY7C1378B
Document #: 38-05435 Rev. *A
Page 3 of 14
Pin Definitions
Name
TQFP
I/O
Description
A0, A1, A
37,36,32,
33,34,35,
44,45,46,
47,48,49,50,
81,82,83,
99,100
Input-
Synchronous
Address Inputs used to select one of the 256K address locations.
Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst
counter.
BW[A:D]
93,94,
95,96
Input-
Synchronous
Byte Write Inputs, active LOW. Qualified with WE to conduct Writes
to the SRAM. Sampled on the rising edge of CLK.
WE
88
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK
if CEN is active LOW. This signal must be asserted LOW to initiate a
Write sequence.
ADV/LD
85
Input-
Synchronous
Advance/Load Input. Used to advance the on-chip address counter
or load a new address. When HIGH (and CEN is asserted LOW) the
internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK
89
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device.
CLK is qualified with CEN. CLK is only recognized if CEN is active
LOW.
CE1
98
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of
CLK. Used in conjunction with CE2 and CE3 to select/deselect the
device.
CE2
97
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of
CLK. Used in conjunction with CE1 and CE3 to select/deselect the
device.
CE3
92
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of
CLK. Used in conjunction with CE1 and CE2 to select/deselect the
device.
OE
86
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Combined with
the synchronous logic block inside the device to control the direction
of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as
input data pins. OE is masked during the data portion of a write se-
quence, during the first clock when emerging from a deselected state,
when the device has been deselected.
CEN
87
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the Clock
signal is recognized by the SRAM. When deasserted HIGH the Clock
signal is masked. Since deasserting CEN does not deselect the de-
vice, CEN can be used to extend the previous cycle when required.
ZZ
64
Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the device in a
non-time critical “sleep” condition with data integrity preserved. During
normal operation, this pin can be connected to VSS or left floating.
DQs
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,
7,8,9,12,
13,18,19,
22,23,24,
25,28,29
I/O-
Synchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, they
deliver the data contained in the memory location specified by A[16:0]
during the clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted
LOW, the pins can behave as outputs. When HIGH, DQs are placed
in a three-state condition. The outputs are automatically three-stated
during the data portion of a Write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
MODE
31
Input
Strap pin
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence.


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