数据搜索系统,热门电子元器件搜索
  Chinese  ▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

CY7C1378B 数据表(PDF) 6 Page - Cypress Semiconductor

部件名 CY7C1378B
功能描述  9-Mbit (256K x 32) Pipelined SRAM with NoBL Architecture
Download  14 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1378B 数据表(HTML) 6 Page - Cypress Semiconductor

Back Button CY7C1378B Datasheet HTML 2Page - Cypress Semiconductor CY7C1378B Datasheet HTML 3Page - Cypress Semiconductor CY7C1378B Datasheet HTML 4Page - Cypress Semiconductor CY7C1378B Datasheet HTML 5Page - Cypress Semiconductor CY7C1378B Datasheet HTML 6Page - Cypress Semiconductor CY7C1378B Datasheet HTML 7Page - Cypress Semiconductor CY7C1378B Datasheet HTML 8Page - Cypress Semiconductor CY7C1378B Datasheet HTML 9Page - Cypress Semiconductor CY7C1378B Datasheet HTML 10Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 14 page
background image
CY7C1378B
Document #: 38-05435 Rev. *A
Page 6 of 14
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Cycle Description Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE
ZZ
ADV/LD
WE
BWx
OE
CEN
CLK
DQ
Deselect Cycle
None
H
L
L
X
X
X
L
L-H
Three-State
Continue
Deselect Cycle
None
X
L
H
X
X
X
L
L-H
Three-State
Read Cycle
(Begin Burst)
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Read Cycle
(Continue Burst)
Next
X
L
H
X
X
L
L
L-H
Data Out (Q)
NOP/Dummy Read
(Begin Burst)
External
L
L
L
H
X
H
L
L-H
Three-State
Dummy Read
(Continue Burst)
Next
X
L
H
X
X
H
L
L-H
Three-State
Write Cycle
(Begin Burst)
External
L
L
L
L
L
X
L
L-H
Data In (D)
Write Cycle
(Continue Burst)
Next
X
L
H
X
L
X
L
L-H
Data In (D)
NOP/WRITE ABORT
(Begin Burst)
None
L
L
L
L
H
X
L
L-H
Three-State
WRITE ABORT
(Continue Burst)
Next
X
L
H
X
H
X
L
L-H
Three-State
IGNORE CLOCK EDGE
(Stall)
Current
X
L
X
X
X
X
H
L-H
-
SNOOZE MODE
None
X
H
X
X
X
X
X
X
Three-State
Notes:
2. X = “Don't Care.” H = HIGH, L = LOW. CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies
that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
3. Write is defined by BW[A:D], and WE. See Write Cycle Descriptions table.
4. When a Write cycle is detected, all I/Os are three-stated, even during Byte Writes.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = Three-state when
OE is inactive or when the device is deselected, and DQs = data when OE is active.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14 


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn