9 / 12 page
CY7C1352B
PRELIMINARY
9
Switching Waveforms
CEN
CLK
ADDRESS
CE
WE &
1a
Data-
In/Out
tCYC
tCH tCL
RA1
tAH
tAS
tWS tWH
tCES tCEH
tCO
Q4
= DON’T CARE
= UNDEFINED
The combination of WE & BWS[1:0] defines a write cycle (see Write Cycle Description table).
D5
In
Out
WA2
RA3
RA4
WA5
RA6
RA7
tCLZ
tDOH
1a
tCHZ
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for
Device
originally
deselected
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW.
Q7
Out
tCHZ
tCENS
tCENH
tDOH
BWS[1:0]
Read/Write/Deselect Sequence
CEN HIGH blocks
Q6
Out
all synchronous inputs
tDS
tDH
OE held LOW.
Q1
Out
Q3
Out
D2
In