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CY7C1352B 数据表(PDF) 5 Page - Cypress Semiconductor

部件名 CY7C1352B
功能描述  256K x 18 Pipilined SRAm with NoBL Architecture
Download  12 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1352B 数据表(HTML) 5 Page - Cypress Semiconductor

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CY7C1352B
PRELIMINARY
5
Burst Write Accesses
The CY7C1352B has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial ad-
dress, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise,
the chip enables (CE1, CE2, and CE3) and WE inputs are ig-
nored and the burst counter is incremented. The correct
BWS[1:0] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Cycle Description Truth Table
[1, 2, 3, 4, 5, 6]
Operation
Address
used
CE
CEN
ADV/
LD/
WE
BWSx
CLK
Comments
Deselected
External
1
0
L
X
X
L-H
I/Os three-state following next rec-
ognized clock.
Suspend
-
X
1
X
X
X
L-H
Clock ignored, all operations
suspended.
Begin Read
External
0
0
0
1
X
L-H
Address latched.
Begin Write
External
0
0
0
0
Valid
L-H
Address latched, data presented
two valid clocks later.
Burst READ
Operation
Internal
X
0
1
X
X
L-H
Burst Read operation. Previous ac-
cess was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of MODE.
Burst WRITE
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous ac-
cess was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of MODE.
Bytes written are determined by
BWS[1:0].
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Write Cycle Descriptions[1, 2]
Function
WE
BWS1
BWS0
Read
1X
X
Write
− No bytes written
0
1
1
Write Byte 0
− (DQ
[7:0] and DP0)0
1
0
Write Byte 1
− (DQ
[15:8] and DP1)0
0
1
Write All Bytes
0
0
0
Notes:
1.
X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx =
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2.
Write is defined by WE and BWS[1:0]. See Write Cycle Description table for details.
3.
The DQ and DP pins are controlled by the current cycle and the OE signal.
4.
CEN=1 inserts wait states.
5.
Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6.
OE assumed LOW.


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