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DRV8714-Q1 数据表(PDF) 46 Page - Texas Instruments |
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DRV8714-Q1 数据表(HTML) 46 Page - Texas Instruments |
46 / 144 page DRV871x-Q1 Powered Off Braking BRAKE 100NŸ 10Ÿ nSLEEP GLx Level Shifter VPOB LS SHx VDS RC Deglitch HIGH LOW ON V5INT GHx 5,6,7,8 DRAIN PVDD VBAT Low IQ Regulator V5INT VPOB VOV VPOB_OV VPOB_VDS FAULT VBAT 10Ÿ 10k MCU Option 1: Internal OV Detect Option 2: External OV Detect Option 3: MCU Enabled Low IQ Option 4: Disable, Tie BRAKE to GND FAULT DRVOFF/nFLT Figure 8-27. Powered Off Braking Note If the powered off braking function is not utilized, the BRAKE pin should be connected directly to GND. 8.3.8.3 Fault Reset (CLR_FLT) The DRV871x-Q1 provides a specific sequence to clear fault conditions from the driver and resume operation. This function is provided through the CLR_FLT register bit. To clear fault reporting the CLR_FLT register bit must be asserted after the fault condition is removed. After being asserted, the driver will clear the fault and reset the CLR_FLT register bit. The function is only available on SPI device variants. On H/W device variants, all faults will automatically recover once the condition is removed. 8.3.8.4 DVDD Logic Supply Power on Reset (DVDD_POR) If at any time the input logic supply voltage on the DVDD pin falls below the VDVDD_POR threshold for longer than the tDVDD_POR_DG time or the nSLEEP pin is asserted low, the device enter its inactive state disabling the gate drivers, charge pump, and protection monitors. Normal operation resumes when the DVDD undervoltage condition is removed or the nSLEEP pin is asserted high. After a DVDD power on reset (POR), the POR register bit is asserted until CLR_FLT is issued. 8.3.8.5 PVDD Supply Undervoltage Monitor (PVDD_UV) If at any time the power supply voltage on the PVDD pin falls below the VPVDD_UV threshold for longer than the tPVDD_UV_DG time, the DRV871x-Q1 detects a PVDD undervoltage condition. After detecting the undervoltage condition, the gate driver pull downs are enabled, charge pump disabled and nFAULT pin, FAULT register bit, and PVDD_UV register bit asserted. On SPI device variants, the PVDD undervoltage monitor can recover in two different modes set through the PVDD_UV_MODE register setting. • Latched Fault Mode: After the undervoltage condition is removed, the fault state remains latched and charge pump disabled until CLR_FLT is issued. • Automatic Recovery Mode: After the undervoltage condition is removed, the nFAULT pin and FAULT register bit are automatically cleared and the charge pump automatically reenabled. The PVDD_UV register bit remains latched until CLR_FLT is issued. DRV8714-Q1, DRV8718-Q1 SLVSEA2 – AUGUST 2020 www.ti.com 46 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DRV8714-Q1 DRV8718-Q1 |
类似零件编号 - DRV8714-Q1 |
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类似说明 - DRV8714-Q1 |
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