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CC3230S 数据表(PDF) 52 Page - Texas Instruments |
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CC3230S 数据表(HTML) 52 Page - Texas Instruments |
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52 / 104 page  8.16.6.1.2 SPI Slave Figure 8-14 shows the timing diagram for the SPI slave. T2 T6 T7 T9 CLK MISO MOSI T8 Figure 8-14. SPI Slave Timing Diagram Section 8.16.6.1.2.1 lists the timing parameters for the SPI slave. 8.16.6.1.2.1 SPI Slave Timing Parameters PARAMETER NUMBER MIN MAX UNIT F(1) Clock frequency at VBAT = 3.3 V 20 MHz Clock frequency at VBAT ≤ 2.1 V 12 T2 Tclk (1) Clock period 50 ns D(1) Duty cycle 45% 55% T6 tIS (1) RX data setup time 4 ns T7 tIH (1) RX data hold time 4 ns T8 tOD (1) TX data output delay 20 ns T9 tOH (1) TX data hold time 24 ns (1) Timing parameter assumes a maximum load of 20 pF at 3.3 V. CC3230S, CC3230SF SWRS226 – FEBRUARY 2020 www.ti.com 52 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CC3230S CC3230SF |
类似零件编号 - CC3230S |
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类似说明 - CC3230S |
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