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IMX8MNCEC 数据表(PDF) 56 Page - NXP Semiconductors |
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IMX8MNCEC 数据表(HTML) 56 Page - NXP Semiconductors |
56 / 89 page i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 0.1, 03/2020 56 NXP Semiconductors Electrical characteristics being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. Figure 33 depicts the timing of the PWM, and Table 43 lists the PWM timing parameters. Figure 33. PWM timing 3.9.9 FlexSPI timing parameters Measurements are with a load of 15 pF and an input slew rate of 1 V/ns. 3.9.9.1 FlexSPI input/read timing There are three sources for the internal sample clock for FlexSPI read data: • Dummy read strobe generated by FlexSPI controller and looped back internally (FlexSPIn_MCR0[RXCLKSRC] = 0x0) • Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1) • Read strobe provided by memory device and input from DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x3) The following sections describe input signal timing for each of these four internal sample clock sources. 3.9.9.1.1 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2 Table 43. PWM output timing parameters ID Parameter Min Max Unit PWM Module Clock Frequency 0 66 (ipg_clk) MHz P1 PWM output pulse width high 12 — ns P2 PWM output pulse width low 12 — ns Table 44. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0 Symbol Parameter Min. Max. Unit Notes — [D:] Frequency of operation — 66 MHz — F1 [D:] Setup time for incoming data 8.67 — ns 1 1 The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be decreased by up to 2ns. F2 [D:] Hold time for incoming data 0 — ns — |
类似零件编号 - IMX8MNCEC |
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类似说明 - IMX8MNCEC |
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