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IMX8MNCEC 数据表(PDF) 45 Page - NXP Semiconductors

部件名 IMX8MNCEC
功能描述  i.MX 8M Nano Applications Processor Datasheet for Consumer Products
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

IMX8MNCEC 数据表(HTML) 45 Page - NXP Semiconductors

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Electrical characteristics
i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 0.1, 03/2020
NXP Semiconductors
45
Figure 18. RGMII transmit signal timing diagram original
Figure 19. RGMII receive signal timing diagram original
Table 38. RGMII signal switching specifications1
1 The timings assume the following configuration:
DDR_SEL = (11)b
DSE (drive-strength) = (111)b
Symbol
Description
Min.
Max.
Unit
Tcyc
2
2 For 10 Mbps and 100 Mbps, T
cyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.
Clock cycle duration
7.2
8.8
ns
TskewT
3
3 For all versions of RGMII prior to 2.0; this implies that PC board design will require clocks to be routed such that an additional
trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value
is unspecified.
Data to clock output skew at transmitter
-500
500
ps
TskewR
3
Data to clock input skew at receiver
1
2.6
ns
Duty_G4
4 Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long
as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned
between.
Duty cycle for Gigabit
45
55
%
Duty_T4
Duty cycle for 10/100T
40
60
%
Tr/Tf
Rise/fall time (20–80%)
0.75
ns


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