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IMX8MNCEC 数据表(PDF) 39 Page - NXP Semiconductors |
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IMX8MNCEC 数据表(HTML) 39 Page - NXP Semiconductors |
39 / 89 page Electrical characteristics i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 0.1, 03/2020 NXP Semiconductors 39 3.9.2.3 HS400 DDR AC timing Figure 14 depicts the timing of HS400 mode, and Table 33 lists the HS400 timing characteristics. Be aware that only data is sampled on both edges of the clock (not applicable to CMD). The CMD input/output timing for HS400 mode is the same as CMD input/output timing for SDR104 mode. Check SD5, SD6, and SD7 parameters in Table 35 SDR50/SDR104 Interface Timing Specification for CMD input/output timing for HS400 mode. Figure 14. HS400 Mode timing SD3 uSDHC Input Setup Time tISU 2.4 — ns SD4 uSDHC Input Hold Time tIH 1.3 — ns Table 33. HS400 interface timing specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock frequency fPP 0 200 MHz SD2 Clock low time tCL 0.46 x tCLK 0.54 x tCLK ns SD3 Clock high time tCH 0.46 x tCLK 0.54 x tCLK ns uSDHC Output/Card Inputs DAT (Reference to SCK) SD4 Output skew from data of edge of SCK tOSkew1 0.45 — ns SD5 Output skew from edge of SCk to data tOSkew2 0.45 — ns uSDHC Input/Card Outputs DAT (Reference to Strobe) Table 32. eMMC5.1/SD3.0 (DDR) interface timing specification (continued) ID Parameter Symbols Min Max Unit SD7 SD1 SD5 SD5 SD6 SCK Output from Strobe Input from uSDHC to eMMC eMMC to uSDHC DAT0 DAT1 DAT7 ... DAT0 DAT1 DAT7 ... SD4 SD4 SD3 SD2 |
类似零件编号 - IMX8MNCEC |
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类似说明 - IMX8MNCEC |
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