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JS28F320J3C-150 数据表(PDF) 49 Page - Intel Corporation

部件名 JS28F320J3C-150
功能描述  Intel StrataFlash Memory (J3)
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

JS28F320J3C-150 数据表(HTML) 49 Page - Intel Corporation

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256-Mbit J3 (x8/x16)
Datasheet
49
13.4
Array Protection
The VPEN signal is a hardware mechanism to prohibit array alteration. When the VPEN voltage is
below the VPENLK voltage, array contents cannot be altered. To ensure a proper erase or program
operation, VPEN must be set to a valid voltage level. To determine the status of an erase or program
operation, poll the Status Register and analyze the bits.
6
Factory
10
00
010
00
7
Factory
10
00
010
01
8
User
1
0
0
0
010
10
9
User
1
0
0
0
010
11
A
User
1
0
0
0
011
00
B
User
1
0
0
0
011
01
C
User
1
0
0
0
011
10
D
User
1
0
0
0
011
11
E
User
1
0
0
0
100
00
F
User
1
0
0
0
100
01
NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register,
i.e.g., A[MAX:9] = 0.
Table 21. Byte-Wide Protection Register Addressing (Sheet 2 of 2)


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