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TLE75242-ESD 数据表(PDF) 24 Page - Infineon Technologies AG |
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TLE75242-ESD 数据表(HTML) 24 Page - Infineon Technologies AG |
24 / 71 page Datasheet 24 Rev. 1.0 2017-11-23 TLE75242-ESD SPIDER+ 12V Power Supply Figure 14 Transition Time diagram 6.2 Reset condition One of the following 3 conditions resets the SPI registers to the default value: • VDD is not present or below the undervoltage threshold VDD(UV) • IDLE pin is set to “low” • a reset command (HWCR.RST set to “1”) is executed – ERRn bits are not cleared by a reset command (for functional safety) – UVRVS and LOPVDD bits are cleared by a reset command In particular, all channels are switched OFF (if there are no input pin set to “high”) and the Input Mapping configuration is reset. 6.2.1 Undervoltage on VS Between VS(UV) and VS(OP) the undervoltage mechanism is triggered. If the device is operative and the supply voltage drops below the undervoltage threshold VS(UV), the logic set the bit UVRVS to “1”. As soon as the supply voltage VS is above the minimum voltage operative threshold VS(OP), the bit UVRVS is set to “0” after the first Standard Diagnosis readout. Undervoltage condition on VS influences the status of the channels, as described in Table 6. Figure 15 sketches the undervoltage behavior (the “VS - VDS” line refers to a channel which is programmed to be ON). OpModesTimings.emf Sleep Idle tSLEEP2IDLE Active Limp Home init tIDLE2SLEEP tACTIVE2IDLE tIDLE2ACTIVE tON tACTIVE2LH tLH2ACTIVE tLH2SLEEP tSLEEP2LH tON Channel ON tACTIVE2SLEEP |
类似零件编号 - TLE75242-ESD |
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类似说明 - TLE75242-ESD |
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