Data Sheet

31

Rev. 1.01

2018-06-14

ITS4075Q-EP-D

75 mΩ Quad Channel Smart High-Side Power Switch

Diagnostic Functions

7.2

Channel Fault Detection

The ITS4075Q-EP-D is equipped with an intelligent channel fault detection system, which allows with the aid

of a microcontroller to identify and communicate the channel on which the fault occurs.

During normal operation the STATUS pin is kept “High” by the external pull-up resistor as shown in Table 6.

If - in case of a fault - the application requires the information on which of the channels the fault occurs when

a “Low” STATUS is flagged, then the microcontroller can be programmed according to the sequence depicted

as an example in Figure 19. The figure shows a case where three channels are active (these are channels 1, 2

and 4). Channel 3 in this example is not switched ON. During normal operation of channels 1, 2 and 4 the

STATUS signal is “High”. If a fault occurs, e.g. at channel 4, the STATUS signal goes “Low” to flag an error to the

microcontroller. The microcontroller, in order to identify on which channel the fault occurs, must send a

“Low” pulse sequentially to the input of each active channel, that is channels 1, 2 and 4 in this case. These

pulses are shown in Figure 19 and their width is denominated

up to 6 µs in order to make sure that the output does not react to this short inversion input level. The STATUS

signal will go to “High” for a short period of time

“Low” pulse from the microcontroller, which in this case is after channel 4 receives a “Low” pulse for a time

In this way, by reading back whether an inversion of the STATUS flag within

able to detect on which channel the fault occurs. Once the microcontroller receives this information it can

start to switch OFF the channel on which the fault occurs (channel 4 in this case) via the corresponding input

pin. For the delay time

account.

Channel fault detection

interrogation time

(Sequential Pulse Width)

3–

6µs

P_7.1.2

STATUS signal “High” valid

window after

channel

40

80

150

µs

5) –

P_7.1.6

Minimum delay between

subsequent

windows.

200

–

–

µs

1) –

P_7.1.8

Maximum delay time between

(“High” to “Low”) on fault

affected channel and STATUS

“High” signal

–8

–µs

1) –

P_7.1.7

1) Not subject to production test; specified by design.

2) This parameter describes the status settling time when a channel is switched on into an already existing overload

condition. This parameter is referenced to the edge of the input pin IN that switches the channel into overload.

3) Levels referenced to device ground.

4) Depends on pull-up circuit that is used within application; maximum ratings of STATUS pin need to be respected.

5) Please refer to “Channel Fault Detection” on Page 31 for more details.

Table 7

Electrical Characteristics: Diagnostic Functions (cont’d)

Typical values are given at

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ.

Max.