PC28F256J3A-115 datasheet(63/72 Pages) INTEL

部件名	PC28F256J3A-115

功能描述	Intel StrataFlash Memory (J3)

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制造商	INTEL [Intel Corporation]

网页	http://www.intel.com

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63 / 72 page

256-Mbit J3 (x8/x16)

Datasheet

63

0606_09

Figure 22. Block Erase Flowchart

Start

Read

Status Register

SR.7 =

Erase Flash

Block(s) Complete

0

1

Full Status

Check if Desired

Suspend Erase

Issue Single Block Erase

Command 20H, Block

Address

Suspend

Erase Loop

Write Confirm D0H

Block Address

Yes

No

Bus

Operation

Command

Comments

Write

Erase Block

Data = 20H

Addr = Block Address

Write (Note 1)

Erase

Confirm

Data = D0H

Addr = X

Read

Status register data

With the device enabled,

OE# low updates SR

Addr = X

Standby

Check SR.7

1 = WSM Ready

0 = WSM Busy

1. The Erase Confirm byte must follow Erase Setup.

This device does not support erase queuing. Please see

Application note AP-646 For software erase queuing

compatibility.

Full status check can be done after all erase and write

sequences complete. Write FFH after the last operation to

reset the device to read array mode.

类似零件编号 - PC28F256J3A-115

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Intel Corporation	PC28F256J3C125	990Kb / 72P	Intel StrataFlash짰 Memory

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