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PC28F256J3A-120 数据表(PDF) 21 Page - Intel Corporation |
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PC28F256J3A-120 数据表(HTML) 21 Page - Intel Corporation |
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21 / 72 page  256-Mbit J3 (x8/x16) Datasheet 21 VPENH VPEN during Block Erase, Program, or Lock-Bit Operations 2.7 3.6 V 3,4 VLKO VCC Lockout Voltage 2.0 V 5 NOTES: 1. Includes STS. 2. Sampled, not 100% tested. 3. Block erases, programming, and lock-bit configurations are inhibited when VPEN ≤ VPENLK, and not guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH (max). 4. Typically, VPEN is connected to VCC (2.7 V–3.6 V). 5. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max). 6. Includes all operational modes of the device including standby and power-up sequences. 7. VCC operating condition for standby has to meet typical operationg coditons. Table 7. DC Voltage Characteristics Symbol Parameter Min Max Unit Test Conditions Notes |
类似零件编号 - PC28F256J3A-120 |
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类似说明 - PC28F256J3A-120 |
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