PC28F256J3C-150 datasheet(35/72 Pages) INTEL

部件名	PC28F256J3C-150

功能描述	Intel StrataFlash Memory (J3)

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制造商	INTEL [Intel Corporation]

网页	http://www.intel.com

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35 / 72 page

256-Mbit J3 (x8/x16)

Datasheet

35

9.2

Device Commands

When the VPEN voltage ≤ VPENLK, only read operations from the Status Register, CFI, identifier

codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program,

and lock-bit configuration operations. Device operations are selected by writing specific

commands into the CUI. Table 14, “Command Bus-Cycle Definitions” on page 35 defines these

commands.

Table 14. Command Bus-Cycle Definitions (Sheet 1 of 2)

Command

Scalable or

Basic

Command

Set

(2)

Bus

Cycles

Req’d.

First Bus Cycle

Second Bus Cycle

Notes

Oper(3)

Addr(4)

Data(5,6)

Oper(3)

Addr(4)

Data(5,6)

Read Array

SCS/BCS

1

Write

X

0xFF

1

Read Identifier Codes

SCS/BCS

≥ 2

Write

X

0X90

Read

IA

ID

1,7

Read Query

SCS

≥ 2

Write

X

0x98

Read

QA

QD

1

Read Status Register

SCS/BCS

2

Write

X

0x70

Read

X

SRD

1,8

Clear Status Register

SCS/BCS

1

Write

X

0x50

1

Write to Buffer

SCS/BCS

> 2

Write

BA

0xE8

Write

BA

N

1,9, 10,

11

Word/Byte Program

SCS/BCS

2

Write

X

0x40 or

0x10

Write

PA

PD

1,12,13

Block Erase

SCS/BCS

2

Write

BA

0x20

Write

BA

0xD0

1,11,12

Block Erase, Program

Suspend

SCS/BCS

1

Write

X

0xB0

1,12,14

Block Erase, Program

Resume

SCS/BCS

1

Write

X

0xD0

1,12

Configuration

SCS

2

Write

X

0xB8

Write

X

CC

1

Set Block Lock-Bit

SCS

2

Write

X

0x60

Write

BA

0x01

1

类似零件编号 - PC28F256J3C-150

制造商	部件名	数据表	功能描述
Intel Corporation	PC28F256J3C125	990Kb / 72P	Intel StrataFlash짰 Memory

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