数据搜索系统,热门电子元器件搜索 |
|
EP2AGX45DF25I5 数据表(PDF) 54 Page - Altera Corporation |
|
EP2AGX45DF25I5 数据表(HTML) 54 Page - Altera Corporation |
54 / 90 page 1–46 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–41 lists the transceiver jitter specifications for all supported protocols for Arria II GZ devices. Sinusoidal jitter tolerance at 3072 Mbps Jitter frequency = 21.8 KHz Pattern = CJPAT > 8.5 > 8.5 > 8.5 > 8.5 UI Jitter frequency = 1843.2 KHz to 20 MHz Pattern = CJPAT > 0.1 > 0.1 > 0.1 > 0.1 UI Notes to Table 1–40: (1) Dedicated refclk pins are used to drive the input reference clocks. The jitter numbers are valid for the stated conditions only. (2) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification. (3) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification. (4) The jitter numbers for PCIe are compliant to the PCIe Base Specification 2.0. (5) The jitter numbers for SRIO are compliant to the RapidIO Specification 1.3. (6) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification. (7) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification. (8) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications. (9) Arria II PCIe receivers are compliant to this specification provided the VTX_CM-DC-ACTIVEIDLE-DELTA of the upstream transmitter is less than 50 mV. (10) The jitter numbers for Serial Advanced Technology Attachment (SATA) are compliant to the Serial ATA Revision 3.0 Specification. (11) The jitter numbers for Common Public Radio Interface (CPRI) are compliant to the CPRI Specification V3.0. (12) The jitter numbers for Open Base Station Architecture Initiative (OBSAI) are compliant to the OBSAI RP3 Specification V4.1. Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 10 of 10) Symbol/ Description Conditions I3 C4 C5, I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 1 of 7) Symbol/ Description Conditions –C3 and –I3 –C4 and –I4 Unit Min Typ Max Min Typ Max SONET/SDH Transmit Jitter Generation (3) Peak-to-peak jitter at 622.08 Mbps Pattern = PRBS15 — — 0.1 — — 0.1 UI RMS jitter at 622.08 Mbps Pattern = PRBS15 — — 0.01 — — 0.01 UI Peak-to-peak jitter at 2488.32 Mbps Pattern = PRBS15 — — 0.1 — — 0.1 UI RMS jitter at 2488.32 Mbps Pattern = PRBS15 — — 0.01 — — 0.01 UI SONET/SDH Receiver Jitter Tolerance (3) Jitter tolerance at 622.08 Mbps Jitter frequency = 0.03 KHz Pattern = PRBS15 > 15 > 15 UI Jitter frequency = 25 KHZ Pattern = PRBS15 > 1.5 > 1.5 UI Jitter frequency = 250 KHz Pattern = PRBS15 > 0.15 > 0.15 UI |
类似零件编号 - EP2AGX45DF25I5 |
|
类似说明 - EP2AGX45DF25I5 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |