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EP1S30F1508I7ES 数据表(PDF) 51 Page - Altera Corporation |
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EP1S30F1508I7ES 数据表(HTML) 51 Page - Altera Corporation |
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51 / 290 page  Altera Corporation 2–27 July 2005 Stratix Device Handbook, Volume 1 Stratix Architecture M512 RAM Block The M512 RAM block is a simple dual-port memory block and is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block contains 576 RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes: ■ Simple dual-port RAM ■ Single-port RAM ■ FIFO ■ ROM ■ Shift register When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. The memory address depths and output widths can be configured as 512 × 1, 256 × 2, 128 × 4, 64 × 8 (64 × 9 bits with parity), and 32 × 16 (32 × 18 bits with parity). Mixed-width configurations are also possible, allowing different read and write widths. Table 2–4 summarizes the possible M512 RAM block configurations. When the M512 RAM block is configured as a shift register block, a shift register of size up to 576 bits is possible. The M512 RAM block can also be configured to support serializer and deserializer applications. By using the mixed-width support in combination with DDR I/O standards, the block can function as a SERDES to support low-speed serial I/O standards using global or regional clocks. See “I/O Structure” on page 2–104 for details on dedicated SERDES in Stratix devices. Table 2–4. M512 RAM Block Configurations (Simple Dual-Port RAM) Read Port Write Port 512 × 1 256 × 2 128 × 4 64 × 8 32 × 16 64 × 9 32 × 18 512 × 1 v v vvv 256 × 2 v v vvv 128 × 4 vvv v 64 × 8 vv v 32 × 16 vvv v 64 × 9 v 32 × 18 v |
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