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EP1S30B1508I7ES 数据表(PDF) 91 Page - Altera Corporation

部件名 EP1S30B1508I7ES
功能描述  Stratix Device Family Data Sheet
Download  290 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1S30B1508I7ES 数据表(HTML) 91 Page - Altera Corporation

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Altera Corporation
2–67
July 2005
Stratix Device Handbook, Volume 1
Stratix Architecture
Multiply-Accumulator Mode
In multiply-accumulator mode (see Figure 2–37), the DSP block drives
multiplied results to the adder/subtractor/accumulator block configured
as an accumulator. You can implement one or two multiply-accumulators
up to 18 × 18 bits in one DSP block. The first and third multiplier sub-
blocks are unused in this mode, because only one multiplier can feed one
of two accumulators. The multiply-accumulator output can be up to 52
bits—a maximum of a 36-bit result with 16 bits of accumulation. The
accum_sload
and overflow signals are only available in this mode.
The addnsub signal can set the accumulator for decimation and the
overflow
signal indicates underflow condition.
Figure 2–37. Multiply-Accumulate Mode
Notes to Figure 2–37:
(1)
These signals are not registered or registered once to match the data path pipeline.
(2)
These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
Two-Multipliers Adder Mode
The two-multipliers adder mode uses the adder/subtractor/accumulator
block to add or subtract the outputs of the multiplier block, which is
useful for applications such as FFT functions and complex FIR filters. A
CLRN
DQ
ENA
CLRN
DQ
ENA
Data A
Data B
Data Out
overflow
Shiftout B
Shiftout A
Shiftin A
Shiftin B
aclr
clock
ena
signa (1)
signb (1)
CLRN
DQ
ENA
CLRN
DQ
ENA
Accumulator
addnsub (2)
signa (2)
signb (2)
accum_sload (2)


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