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EP1S30F1508I5ES 数据表(PDF) 98 Page - Altera Corporation |
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EP1S30F1508I5ES 数据表(HTML) 98 Page - Altera Corporation |
98 / 290 page 2–74 Altera Corporation Stratix Device Handbook, Volume 1 July 2005 PLLs & Clock Networks There are 16 dedicated clock pins (CLK[15..0]) to drive either the global or regional clock networks. Four clock pins drive each side of the device, as shown in Figure 2–42. Enhanced and fast PLL outputs can also drive the global and regional clock networks. Global Clock Network These clocks drive throughout the entire device, feeding all device quadrants. The global clock networks can be used as clock sources for all resources within the device—IOEs, LEs, DSP blocks, and all memory blocks. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The global clock networks can also be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 2–42 shows the 16 dedicated CLK pins driving global clock networks. |
类似零件编号 - EP1S30F1508I5ES |
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类似说明 - EP1S30F1508I5ES |
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