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EP1S30F1508I5ES 数据表(PDF) 55 Page - Altera Corporation |
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EP1S30F1508I5ES 数据表(HTML) 55 Page - Altera Corporation |
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55 / 290 page  Altera Corporation 2–31 July 2005 Stratix Device Handbook, Volume 1 Stratix Architecture The memory address depths and output widths can be configured as 4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or 256 × 18 bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit configuration is not available in the true dual-port mode. Mixed-width configurations are also possible, allowing different read and write widths. Tables 2–5 and 2–6 summarize the possible M4K RAM block configurations. When the M4K RAM block is configured as a shift register block, you can create a shift register up to 4,608 bits (w × m × n). Table 2–5. M4K RAM Block Configurations (Simple Dual-Port) Read Port Write Port 4K × 12K × 21K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36 4K × 1 v vvv v v 2K × 2 v vvv v v 1K × 4 v vvv v v 512 × 8 v vvv v v 256 × 16 v vvv v v 128 × 32 v vvv v v 512 × 9 vv v 256 × 18 vv v 128 × 36 vv v Table 2–6. M4K RAM Block Configurations (True Dual-Port) Port A Port B 4K × 12K × 21K × 4 512 × 8 256 × 16 512 × 9 256 × 18 4K × 1 vvvvv 2K × 2 vvvvv 1K × 4 vvvvv 512 × 8 vvvvv 256 × 16 vvvvv 512 × 9 vv 256 × 18 vv |
类似零件编号 - EP1S30F1508I5ES |
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类似说明 - EP1S30F1508I5ES |
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