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EP1S30F1508C5ES 数据表(PDF) 26 Page - Altera Corporation |
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EP1S30F1508C5ES 数据表(HTML) 26 Page - Altera Corporation |
26 / 290 page 2–2 Altera Corporation Stratix Device Handbook, Volume 1 July 2005 Functional Description dedicated clocks, these registers provide exceptional performance and interface support with external memory devices such as DDR SDRAM, FCRAM, ZBT, and QDR SRAM devices. High-speed serial interface channels support transfers at up to 840 Mbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure 2–1 shows an overview of the Stratix device. Figure 2–1. Stratix Block Diagram M512 RAM Blocks for Dual-Port Memory, Shift Registers, & FIFO Buffers DSP Blocks for Multiplication and Full Implementation of FIR Filters M4K RAM Blocks for True Dual-Port Memory & Other Embedded Memory Functions IOEs Support DDR, PCI, GTL+, SSTL-3, SSTL-2, HSTL, LVDS, LVPECL, PCML, HyperTransport & other I/O Standards IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs LABs LABs IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs IOEs IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs DSP Block M-RAM Block |
类似零件编号 - EP1S30F1508C5ES |
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类似说明 - EP1S30F1508C5ES |
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