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EP1S30F1508C5ES 数据表(PDF) 17 Page - Altera Corporation |
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EP1S30F1508C5ES 数据表(HTML) 17 Page - Altera Corporation |
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17 / 290 page  Altera Corporation Section I–7 Stratix Device Family Data Sheet 4 October 2003, v2.1 ● Added -8 speed grade information. ● Updated performance information in Table 4–36. ● Updated timing information in Tables 4–55 through 4–96. ● Updated delay information in Tables 4–103 through 4–108. ● Updated programmable delay information in Tables 4–100 and 4–103. July 2003, v2.0 ● Updated clock rates in Tables 4–114 through 4–123. ● Updated speed grade information in the introduction on page 4-1. ● Corrected figures 4-1 & 4-2 and Table 4-9 to reflect how VID and VOD are specified. ● Added note 6 to Table 4-32. ● Updated Stratix Performance Table 4-35. ● Updated EP1S60 and EP1S80 timing parameters in Tables 4-82 to 4- 93. The Stratix timing models are final for all devices. ● Updated Stratix IOE programmable delay chains in Tables 4-100 to 4- 101. ● Added single-ended I/O standard output pin delay adders for loading in Table 4-102. ● Added spec for FPLL[10..7]CLK pins in Tables 4-104 and 4-107. ● Updated high-speed I/O specification for J=2 in Tables 4-114 and 4- 115. ● Updated EPLL specification and fast PLL specification in Tables 4- 116 to 4-120. 5 September 2004, v2.1 ● Updated reference to device pin-outs on page 5–1 to indicate that device pin-outs are no longer included in this manual and are now available on the Altera web site. April 2003, v1.0 ● No new changes in Stratix Device Handbook v2.0. Chapter Date/Version Changes Made |
类似零件编号 - EP1S30F1508C5ES |
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类似说明 - EP1S30F1508C5ES |
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