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EP1S30F1508C5ES 数据表(PDF) 12 Page - Altera Corporation |
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EP1S30F1508C5ES 数据表(HTML) 12 Page - Altera Corporation |
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12 / 290 page  Section I–2 Altera Corporation Stratix Device Family Data Sheet Stratix Device Handbook, Volume 1 2 July 2005 v3.2 ● Added “Clear Signals” section. ● Updated “Power Sequencing & Hot Socketing” section. ● Format changes. September 2004, v3.1 ● Updated fast regional clock networks description on page 2–73. ● Deleted the word preliminary from the “specification for the maximum time to relock is 100 µs” on page 2–90. ● Added information about differential SSTL and HSTL outputs in “External Clock Outputs” on page 2–92. ● Updated notes in Figure 2–55 on page 2–93. ● Added information about m counter to “Clock Multiplication & Division” on page 2–101. ● Updated Note 1 in Table 2–58 on page 2–101. ● Updated description of “Clock Multiplication & Division” on page 2–88. ● Updated Table 2–22 on page 2–102. ● Added references to AN 349 and AN 329 to “External RAM Interfacing” on page 2–115. ● Table 2–25 on page 2–116: updated the table, updated Notes 3 and 4. Notes 4, 5, and 6, are now Notes 5, 6, and 7, respectively. ● Updated Table 2–26 on page 2–117. ● Added information about PCI Compliance to page 2–120. ● Table 2–32 on page 2–126: updated the table and deleted Note 1. ● Updated reference to device pin-outs now being available on the web on page 2–130. ● Added Notes 4 and 5 to Table 2–36 on page 2–130. ● Updated Note 3 in Table 2–37 on page 2–131. ● Updated Note 5 in Table 2–41 on page 2–135. April 2004, v3.0 ● Added note 3 to rows 11 and 12 in Table 2–18. ● Deleted “Stratix and Stratix GX Device PLL Availability” table. ● Added I/O standards row in Table 2–28 that support max and min strength. ● Row clk [1,3,8,10] was removed from Table 2–30. ● Added checkmarks in Enhanced column for LVPECL, 3.3-V PCML, LVDS, and HyperTransport technology rows in Table 2–32. ● Removed the Left and Right I/O Banks row in Table 2–34. ● Changed RCLK values in Figures 2–50 and 2–51. ● External RAM Interfacing section replaced. November 2003, v2.2 ● Added 672-pin BGA package information in Table 2–37. ● Removed support for series and parallel on-chip termination. ● Termination Technology renamed differential on-chip termination. ● Updated the number of channels per PLL in Tables 2-38 through 2- 42. ● Updated Figures 2–65 and 2–67. October 2003, v2.1 ● Updated DDR I information. ● Updated Table 2–22. ● Added Tables 2–25, 2–29, 2–30, and 2–72. ● Updated Figures 2–59, 2–65, and 2–67. ● Updated the Lock Detect section. Chapter Date/Version Changes Made |
类似零件编号 - EP1S30F1508C5ES |
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类似说明 - EP1S30F1508C5ES |
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