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EP1S30F1508C5ES 数据表(PDF) 75 Page - Altera Corporation |
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EP1S30F1508C5ES 数据表(HTML) 75 Page - Altera Corporation |
75 / 290 page Altera Corporation 2–51 July 2005 Stratix Device Handbook, Volume 1 Stratix Architecture Single-Port Mode The memory blocks also support single-port mode, used when simultaneous reads and writes are not required. See Figure 2–28. A single block in a memory block can support up to two single-port mode RAM blocks in the M4K RAM blocks if each RAM block is less than or equal to 2K bits in size. Figure 2–28. Single-Port Mode Note (1) Note to Figure 2–28: (1) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. 8 D ENA Q D ENA Q D ENA Q D ENA Q data[ ] address[ ] RAM/ROM 256 × 16 512 × 8 1,024 × 4 2,048 × 2 4,096 × 1 Data In Address Write Enable Data Out outclken inclken inclock outclock Write Pulse Generator wren 8 LAB Row Clocks To MultiTrack Interconnect |
类似零件编号 - EP1S30F1508C5ES |
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类似说明 - EP1S30F1508C5ES |
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