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MSP430FG479 数据表(PDF) 43 Page - Texas Instruments |
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MSP430FG479 数据表(HTML) 43 Page - Texas Instruments |
43 / 97 page 43 MSP430FG479, MSP430FG478, MSP430FG477 www.ti.com SLAS580E – OCTOBER 2008 – REVISED MAY 2020 Submit Documentation Feedback Product Folder Links: MSP430FG479 MSP430FG478 MSP430FG477 Specifications Copyright © 2008–2020, Texas Instruments Incorporated (1) The DCO wake-up time must be considered in LPM3 or LPM4 for baud rates above 1 MHz. (2) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. 5.46 USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fUSCI USCI input clock frequency Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ±10% fSYSTEM MHz fBITCLK BITCLK clock frequency (equals baud rate in MBaud)(1) 2.2 V, 3 V 2 MHz tτ UART receive deglitch time UART(2) 2.2 V 50 150 600 ns 3 V 50 100 600 (1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)) For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. 5.47 USCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-31 and Figure 5-32) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT fUSCI USCI input clock frequency SMCLK, ACLK Duty cycle = 50% ±10% fSYSTEM MHz tSU,MI SOMI input data setup time 2.2 V 110 ns 3 V 75 tHD,MI iSOMI input data hold time 2.2 V 0 ns 3 V 0 tVALID,MO SIMO output data valid time UCLK edge to SIMO valid, CL = 20 pF 2.2 V 30 ns 3 V 20 (1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)) For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master. 5.48 USCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-33 and Figure 5-34) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT tSTE,LEAD STE lead time STE low to clock 2.2 V, 3 V 50 ns tSTE,LAG STE lag time Last clock to STE high 2.2 V, 3 V 10 ns tSTE,ACC STE access time STE low to SOMI data out 2.2 V, 3 V 50 ns tSTE,DIS STE disable time STE high to SOMI high impedance 2.2 V, 3 V 50 ns tSU,SI SIMO input data setup time 2.2 V 20 ns 3 V 15 tHD,SI SIMO input data hold time 2.2 V 10 ns 3 V 10 tVALID,SO SOMI output data valid time UCLK edge to SOMI valid, CL = 20 pF 2.2 V 75 110 ns 3 V 50 75 |
类似零件编号 - MSP430FG479 |
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类似说明 - MSP430FG479 |
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