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MSP430F2619 数据表(PDF) 71 Page - Texas Instruments |
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MSP430F2619 数据表(HTML) 71 Page - Texas Instruments |
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71 / 120 page  71 MSP430F2619, MSP430F2618, MSP430F2617, MSP430F2616 MSP430F2419, MSP430F2418, MSP430F2417, MSP430F2416 www.ti.com SLAS541L – JUNE 2007 – REVISED MAY 2020 Submit Documentation Feedback Product Folder Links: MSP430F2619 MSP430F2618 MSP430F2617 MSP430F2616 MSP430F2419 MSP430F2418 MSP430F2417 MSP430F2416 Detailed Description Copyright © 2007–2020, Texas Instruments Incorporated 6.9.10 Timer_B7 Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 supports multiple capture/compares, PWM outputs, and interval timing (see Table 6-13). Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-13. Timer_B3, Timer_B7 Signal Connections INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER ZCA, ZQW PM, PN PM, PN ZCA, ZQW K11 - P4.7 43 - P4.7 TBCLK TBCLK Timer NA ACLK ACLK SMCLK SMCLK K11 - P4.7 43 - P4.7 TBCLK INCLK M9 - P4.0 36 - P4.0 TB0 CCI0A CCR0 TB0 36 - P4.0 M9 - P4.0 M9- P4.0 36 - P4.0 TB0 CCI0B ADC12 (internal) DVSS GND DVCC VCC J9 - P4.1 37 - P4.1 TB1 CCI1A CCR1 TB1 37 - P4.1 J9 - P4.1 J9 - P4.1 37 - P4.1 TB1 CCI1B ADC12 (internal) DVSS GND DVCC VCC M10 - P4.2 38 - P4.2 TB2 CCI2A CCR2 TB2 38 - P4.2 M10 - P4.2 M10 - P4.2 38 - P4.2 TB2 CCI2B DAC_0 (internal) DVSS GND DAC_1 (internal) DVCC VCC L10 - P4.3 39 - P4.3 TB3 CCI3A CCR3 TB3 39 - P4.3 L10 - P4.3 L10 - P4.3 39 - P4.3 TB3 CCI3B DVSS GND DVCC VCC M11 - P4.4 40 - P4.4 TB4 CCI4A CCR4 TB4 40 - P4.4 M11 - P4.4 M11 - P4.4 40 - P4.4 TB4 CCI4B DVSS GND DVCC VCC M12 - P4.5 41 - P4.5 TB5 CCI5A CCR5 TB5 41 - P4.5 M12 - P4.5 M12 - P4.5 41 - P4.5 TB5 CCI5B DVSS GND DVCC VCC L12 - P4.6 42 - P4.6 TB6 CCI6A CCR6 TB6 42 - P4.6 L12 - P4.6 ACLK (internal) CCI6B DVSS GND DVCC VCC |
类似零件编号 - MSP430F2619 |
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类似说明 - MSP430F2619 |
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