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SAA32M4 数据表(PDF) 2 Page - List of Unclassifed Manufacturers

部件名 SAA32M4
功能描述  DOUBLE DATA RATE (DDR) SDRAM
Download  13 Pages
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制造商  ETC1 [List of Unclassifed Manufacturers]
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标志 ETC1 - List of Unclassifed Manufacturers

SAA32M4 数据表(HTML) 2 Page - List of Unclassifed Manufacturers

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128Mb: x4, x8, x16
DDR SDRAM
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
2
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
© 2001, 2002, 2004 SpecTek
GENERAL DESCRIPTION
The 128Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing 134,217,728 bits.
It is internally configured as a quad-bank DRAM.
The 128Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The double data
rate architecture is essentially a 2
n-prefetch architecture with
an interface designed to transfer two data words per clock
cycle at the I/O pins. A single read or write access for the
128Mb DDR SDRAM effectively consists of a single 2
n-bit
wide, one-clock-cycle data transfer at the internal DRAM core
and two corresponding
n-bit wide, one-half-clock-cycle data
transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR SDRAM
during READs and by the memory controller during WRITEs.
DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs. The x16 offering has two data strobes,
one for the lower byte and one for the upper byte.
The 128Mb DDR SDRAM operates from a differential
clock (CK and CK#); the crossing of CK going HIGH and
CK# going LOW will be referred to as the positive edge of
CK. Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be
accessed. The address bits registered coincident with the
READ or WRITE command are used to select the bank and
the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or
WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As
with
standard
SDR
SDRAMs,
the
pipelined,
multibank
architecture
of
DDR
SDRAMs
allows
for
concurrent
operation,
thereby
providing
high
effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-
saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All full drive strength outputs
are SSTL_2, Class II compatible.
NOTE 1: The functionality and the timing specifications discussed
in this data sheet are for the DLL-enabled mode of
operation.
NOTE 2: Throughout the data sheet, the various figures and text
refer to DQs as “DQ.” The DQ term is to be interpreted as
any and all DQ collectively, unless specifically stated
otherwise.
Additionally, the x16 is divided in to two bytes — the
lower byte and upper byte. For the lower byte (DQ0
through DQ7) DM refers to LDM and DQS refers to
LDQS; and for the upper byte (DQ8 through DQ15) DM
refers to UDM and DQS refers to UDQS.
___________________________________________________
ABSOLUTE MAXIMUM RATINGS*
VDD Supply Voltage
Relative to VSS .....................................-1V to +3.6V
VDDQ Supply
Voltage Relative to VSS ......................... -1V to +3.6V
VREF and Inputs Voltage
Relative to VSS .....................................-1V to +3.6V
I/O Pins Voltage
Relative to VSS ..........................-0.5V to VDDQ +0.5V
Operating Temperature, TA (ambient) .....…. 25°C to +70°C
Storage Temperature (plastic) ....….......... -55°C to +150°C
Power Dissipation ..................................................1W
Short Circuit Output Current .............................…..50mA
Disclaimer:
Except as specifically provided in this document,
SpecTek makes no warranties, expressed or implied,
including, but not limited to, any implied warranties of
merchantability or fitness for a particular purpose.
Any claim against SpecTek must be made within 1
year from the date of shipment from SpecTek, and
SpecTek has no liability thereafter. Any liability is limited
to replacement of the defective items or return of
amounts paid for defective items (at buyer’s election). In
no event will SpecTek be responsible for special,
indirect, consequential or incidental damages, even if
SpecTek has been advised for the possibility of such
damages. SpecTek’s liability from any cause pursuant
to this specification shall be limited to general monetary
damages in an amount not to exceed the total purchase
price of the products covered by this specification,
regardless of the form in which legal or equitable action
may be brought against SpecTek.


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