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MC74HC175ADTR2 数据表(PDF) 4 Page - ON Semiconductor |
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MC74HC175ADTR2 数据表(HTML) 4 Page - ON Semiconductor |
4 / 8 page MC74HC175A http://onsemi.com 4 TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25 _C v 85_C v 125_C Unit tsu Minimum Setup Time, Data to Clock (Figure 3) 2.0 3.0 4.5 6.0 100 45 20 17 125 65 25 21 150 85 30 26 ns th Minimum Hold Time, Clock to Data (Figure 3) 2.0 3.0 4.5 6.0 5 3 3 3 5 3 3 3 5 3 3 3 ns trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 3.0 4.5 6.0 100 45 20 17 125 65 25 21 150 85 30 26 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 3.0 4.5 6.0 80 45 16 14 100 65 20 17 120 85 24 20 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 3.0 4.5 6.0 80 45 16 14 100 65 20 17 120 85 24 20 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). |
类似零件编号 - MC74HC175ADTR2 |
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类似说明 - MC74HC175ADTR2 |
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