MC74AC573, MC74ACT573

http://onsemi.com

2

TRUTH TABLE

Inputs

Outputs

OE

LE

L

H

H

H

L

H

L

L

L

L

X

H

X

X

Z

H = HIGH Voltage Level

L = LOW Voltage Level

Z = High Impedance

X = Immaterial

Functional Description

The MC74AC573/74ACT574 contains eight D−type

latches with 3−state output buffers. When the Latch Enable

In this condition the latches are transparent, i.e., a latch

output will change state each time its D input changes. When

LE is LOW the latches store the information that was present

on the D inputs a setup time preceding the HIGH−to−LOW

transition of LE. The 3−state buffers are controlled by the

Output Enable (OE) input. When OE is LOW, the buffers are

enabled. When OE is HIGH the buffers are in the high

impedance mode but this does not interfere with entering

new data into the latches.

Figure 3. Logic Diagram

D

LE

Q

D

LE

Q

D

LE

Q

D

LE

Q

D

LE

Q

D

LE

Q

D

LE

Q

D

LE

Q

LE

OE

NOTE:

That this diagram is provided only for the understanding of logic

operations and should not be used to estimate propagation delays.