1

INDUSTRIALTEMPERATURERANGE

QS5919T

LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

R

D

Q

R

D

Q

R

D

Q

R

D

Q

R

D

Q

R

D

Q

R

D

Q

Q/2

Q

OE/R ST

0

1

1

0

/2

VCO

LO O P

FIL TER

PH ASE

DETECTO R

1

0

FR EQ _SEL

REF_SEL

LO C K

FEE D BACK

PLL_E N

2xQ

PE

SEPTEMBER 2000

2000

Integrated Device Technology, Inc.

DSC-5815/-

c

QS5919T

INDUSTRIAL TEMPERATURE RANGE

LOW SKEW TTL PLL

CLOCK DRIVER WITH

INTEGRATED LOOP FILTER

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

The QS5919T Clock Driver uses an internal phase locked loop (PLL)

to lock low skew outputs to one of two reference clock inputs. Eight outputs

an internal RC filter which provides excellent jitter characteristics and

eliminates the need for external components. Various combinations of

feedback and a divide-by-2 in the VCO path allow applications to be

customized for linear VCO operation over a wide range of input SYNC

frequencies. The PLL can also be disabled by the PLL_EN signal to allow

low frequency or DC testing. The LOCK output asserts to indicate when

phase lock has been achieved. The QS5919T is designed for use in high-

performance workstations, multi-board computers, networking hardware,

and mainframe systems. Several can be used in parallel or scattered

throughout a system for guaranteed low skew, system-wide clock distribu-

tion networks.

For more information on PLL clock driver products, see Application Note

AN-227.

FEATURES:

•

5V operation

•

Low noise TTL level outputs

•

•

2xQ output, Q outputs, Q output, Q/2 output

•

Outputs 3-state and reset while OE/RST low

•

PLL disable feature for low frequency testing

•

Internal loop filter RC network

•

Functional equivalent to Motorola MC88915

•

Positive or negative edge synchronization (PE)

•

Balanced drive outputs ±24mA

•

160MHz maximum frequency (2xQ output)

•

Available in QSOP and PLCC packages