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CS42438-DMZR 数据表(PDF) 7 Page - Cirrus Logic

部件名 CS42438-DMZR
功能描述  108 dB, 192 kHz 6-in, 8-out TDM CODEC
Download  64 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS42438-DMZR 数据表(HTML) 7 Page - Cirrus Logic

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7
1.1
Digital I/O Pin Characteristics
Various pins on the CS42438 are powered from separate power supply rails. The logic level for each input
should adhere to the corresponding power rail and should not exceed the maximum ratings.
AUX_SCLK
16
Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface.
AUX_SDIN
17
Auxiliary Serial Input (Input) - The CS42438 provides an additional serial input for two’s comple-
ment serial audio data.
AOUT1 +,-
AOUT2 +,-
AOUT3 +,-
AOUT4 +,-
AOUT5 +,-
AOUT6 +,-
20,19
21,22
24,23
25,26
28,27
29,30
Differential Analog Output (Output) - The full-scale differential analog output level is specified in
the Analog Characteristics specification table. Each positive leg of the differential outputs may also
be used single-ended.
AGND
35,48 Analog Ground (Input) -
VQ
36
Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
VA
37,46 Analog Power (Input) - Positive power supply for the analog section.
AIN1 +,-
AIN2 +,-
AIN3 +,-
AIN4 +,-
AIN5 +,-
AIN6 +,-
39,38
41,40
43,42
45,44
50,49
52,51
Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-
tors. The full-scale input level is specified in the Analog Characteristics specification table. Single-
ended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled.
Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to com-
mon mode. See below for a description of AIN5-AIN6 in Single-Ended Mode.
AIN5 A,B
AIN6 A,B
50,49
52,51
Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allows selec-
tion between 2 channels for both analog inputs AIN5 and AIN6 (see section 7.6.6-7.6.8 for details).
The unused leg of each input is internally connected to common mode. The full-scale input level is
specified in the Analog Characteristics specification table.
FILT+
47
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-
cuits.
Power
Rail
Pin Name
SW/(HW)
I/O
Driver
Receiver
VLC
RST
Input
-
1.8 V - 5.0 V, CMOS
SCL/CCLK
(AIN5_MUX)
Input
-
1.8 V - 5.0 V, CMOS, with Hysteresis
SDA/CDOUT
(AIN6_MUX)
Input/
Output
1.8 V - 5.0 V, CMOS/Open Drain
1.8 V - 5.0 V, CMOS, with Hysteresis
AD0/CS
(MFREQ)
Input
-
1.8 V - 5.0 V, CMOS
AD1/CDIN
(ADC3_HPF)
Input
-
1.8 V - 5.0 V, CMOS
VLS
MCLK
Input
-
1.8 V - 5.0 V, CMOS
LRCK
Input
-
1.8 V - 5.0 V, CMOS
SCLK
Input
-
1.8 V - 5.0 V, CMOS
ADC_SDOUT
(ADC3_SINGLE)
Input/
Output
1.8 V - 5.0 V, CMOS
-
DAC_SDIN
Input
-
1.8 V - 5.0 V, CMOS
AUX_LRCK
Output
1.8 V - 5.0 V, CMOS
-
AUX_SCLK
Output
1.8 V - 5.0 V, CMOS
-
AUX_SDIN
Input
-
1.8 V - 5.0 V, CMOS
Table 1. I/O Power Rails


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