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SA2400ABE 数据表(PDF) 10 Page - NXP Semiconductors

部件名 SA2400ABE
功能描述  Single chip transceiver for 2.45 GHz ISM band
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

SA2400ABE 数据表(HTML) 10 Page - NXP Semiconductors

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Philips Semiconductors
Product data
SA2400A
Single chip transceiver for 2.45 GHz ISM band
2002 Nov 04
10
9. SA2400A RECEIVER
The baseband output signal extends from DC to 8 MHz, and the out-of-band frequency begins from 11 MHz. The modulated test signal used is
11 Msymbols/sec QPSK with raised cosine filtering (50% excess bandwidth for 11 Msymbols/sec). The LO frequency is the same as the
Receiver channel center frequency, as the IF output is at 0 Hz.
Table 6. SA2400A Receiver properties
Tamb = 25 °C; VCC = 3.3 V; fLO = 2.45 GHz.
Specification
Conditions
Min
Typ
Max
Units
RF input frequency range
Typical
2.4
2.5
GHz
S11 (RF input)
Incl balun+matching. 50
Ω unbalanced. Note 3.
LNA in high gain (see reg. description 0x06)
–10
dB
LNA in low gain
–7
dB
Maximum Rx voltage gain
RF input to I or Q outputs
90
93
dB
Max RF input level
Including application, AGCTARGET = +5. Note 1.
–10
dBm
To maintain nominal IQ output levels as defined
below (“nominal I and Q output voltage”)
–20
dBm
IQ Output DC error (relative to signal,
5
µs after AGC set)
–80 dBm < Pinput < –20 dBm, 1 MHz sinewave
output. Note 3.
–20
dBc
AGC settling time
(indicated by AGC_SET digital
output)
Initiated by AGC_RESET input. Constant RF input
within this settling time. Begins after TX to RX
switching time. Measured from AGC_RESET 0–1
transition. AGC delay registers (0x05) at default or
smaller values. Note 2.
a) First instance
8
µs
b) 2nd or subsequent instances
11
µs
AGC Max Gain settling time
AGC forced to GMAX by:
a) TX to RX mode transition.
(measured after 5
µs TX–RX settling time).
0
µs
b) Pulse on AGC_RESET pin
(measured from end of programming)
3
µs
Note 2.
AGC Max Gain adjustment range
Note 2.
54 to 85, in steps of 1
dB
AGC error (I, Q signal levels)
RF input between –75 to –20 dBm. AGC_RESET
used. AGC delay registers (0x05) at default values.
a) Random (varies each AGC cycle)
–3
3
dB
b) Slow (varies with VCC, Temperature).
–1
1
dB
c) Static (fixed, part to part)
–1
1
dB
DC cancellation time
( ft
AGCRESET)
With constant RF input during this time. Note 3.
(after AGCRESET)
a) DC offset < 50% of output signal level
8
µs
b) DC offset <10% of output signal level
13
µs
TX to RX switching time
Output signal within 1 dB of final value,
frequency error within 25 ppm of final value. Note 3.
3
3.5
µs
Noise Figure
(I
l b l
t hi
)
Less than the piece-wise linear interpolation. Note 3.
(Incl balun+matching)
Pinput = –85 dBm (LNA in high gain mode)
7.5
9
dB
–75 dBm
7.5
9
dB
–60 dBm (LNA in low gain mode)
24
25
dB
–45 dBm
24
25
dB
Input IP3
(50
Ω source resistance)
2 interfering tones of power Pinterferer each, at 13
and 23 MHz offsets from LO.
IP3 to be more than the piece-wise linear
interpolation:
Pinterferer = –39 dBm
–5
1
dBm
1 dB compression of wanted signal
Including matching, receiver at minimum gain.
–10
0
dBm
Desens by jammer
–45 dBm wanted signal at 1 MHz offset, +40 dBc
jammer at 25 MHz offset. Note 3.
1
dB


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