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CS5342-CZZ 数据表(PDF) 11 Page - Cirrus Logic |
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CS5342-CZZ 数据表(HTML) 11 Page - Cirrus Logic |
11 / 22 page CS5342 DS608PP2 11 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF) * For a description of Speed Modes, please refer to Table 1 on page 15 Notes: 9. SCLK must be derived synchronously from MCLK and the ratio of SCLK/LRCK must be equal to 48. Parameter Symbol Min Typ Max Unit MCLK Specifications MCLK Period tclkw 26 - 31 ns 52 - 1303 ns MCLK Pulse Duty Cycle 40 - 60 % Master Mode SCLK falling to LRCK tmslr -20 - 20 ns SCLK falling to SDOUT valid tsdo - - 32 ns SCLK Duty Cycle Single-Speed Double-Speed Quad-Speed - - - 50 50 33 - - - % % % Slave Mode Single Speed* LRCK Duty Cycle 40 - 60 % SCLK Period tsclkw 290 - - ns SCLK Duty Cycle 45 - 55 % SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5- - ns SCLK falling to LRCK edge tslrd -20 - 20 ns Double Speed* LRCK Duty Cycle 40 - 60 % SCLK Period (Note 9) tsclkw 193 - - ns SCLK Duty Cycle 45 - 55 % SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5- - ns SCLK falling to LRCK edge tslrd -20 - 20 ns Quad Speed* (Note 2) LRCK Duty Cycle 40 - 60 % SCLK Period (Note 9) tsclkw 104 - - ns SCLK Duty Cycle 40 - 50 % SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5- - ns SCLK falling to LRCK edge tslrd -8 - 8 ns |
类似零件编号 - CS5342-CZZ |
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类似说明 - CS5342-CZZ |
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