数据搜索系统,热门电子元器件搜索
  Chinese  ▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

CY7C1353F 数据表(PDF) 5 Page - Cypress Semiconductor

部件名 CY7C1353F
功能描述  4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
Download  13 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1353F 数据表(HTML) 5 Page - Cypress Semiconductor

  CY7C1353F Datasheet HTML 1Page - Cypress Semiconductor CY7C1353F Datasheet HTML 2Page - Cypress Semiconductor CY7C1353F Datasheet HTML 3Page - Cypress Semiconductor CY7C1353F Datasheet HTML 4Page - Cypress Semiconductor CY7C1353F Datasheet HTML 5Page - Cypress Semiconductor CY7C1353F Datasheet HTML 6Page - Cypress Semiconductor CY7C1353F Datasheet HTML 7Page - Cypress Semiconductor CY7C1353F Datasheet HTML 8Page - Cypress Semiconductor CY7C1353F Datasheet HTML 9Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 13 page
background image
CY7C1353F
Document #: 38-05212 Rev. *B
Page 5 of 13
BW[A:B] inputs must be driven in each cycle of the burst write,
in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for
the duration of tZZREC after the ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Interleaved Burst Address Table (MODE =
Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Snooze mode standby current
ZZ > VDD − 0.2V
40
mA
tZZS
Device operation to ZZ
ZZ > VDD − 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
tZZI
ZZ active to snooze current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ inactive to exit snooze current
This parameter is sampled
0
ns
Truth Table [2, 3, 4, 5, 6, 7, 8]
Operation
ADDRESS
Used
CE1
CE2 CE3
ZZ
ADV/LD
WE
BWX OE CEN CLK
DQ
Deselect Cycle
None
H
X
X
L
L
X
X
X
L
L->H
three-state
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H
three-state
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H
three-state
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H
three-state
READ Cycle
(Begin Burst)
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
READ Cycle
(Continue Burst)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
NOP/DUMMY READ
(Begin Burst)
External
L
H
L
L
L
H
X
H
L
L->H
three-state
DUMMY READ
(Continue Burst)
Next
X
X
X
L
H
X
X
H
L
L->H
three-state
WRITE Cycle
(Begin Burst)
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
Notes:
2. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BW[A:B], and WE. See truth table for Read/Write.
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQs and DQP[A:B] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = Three-state when
OE is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13 


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn