AM41DL6408H8H70IS datasheet(5/66 Pages) AMD

部件名	AM41DL6408H8H70IS

功能描述	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

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制造商	AMD [Advanced Micro Devices]

网页	http://www.amd.com

标志

5 / 66 page

November 24, 2003

Am41DL6408H

3

ADV ANCE

I N FO RMAT I O N

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5

Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Device Bus Operations—Flash Word Mode, CIOf = V

IH;

SRAM Word Mode, CIOs = V

CC ..................................................... 10

Table 2. Device Bus Operations—Flash Word Mode, CIOf = V

IH;

SRAM Byte Mode, CIOs = V

SS

......................................................11

Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V

SS;

SRAM Word Mode, CIOs = V

CC .....................................................12

Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V

IL; SRAM

Byte Mode, CIOs = V

SS ..................................................................13

Word/Byte Configuration ........................................................ 13

Requirements for Reading Array Data ................................... 13

Writing Commands/Command Sequences ............................ 14

Accelerated Program Operation .......................................... 14

Autoselect Functions ........................................................... 14

Simultaneous Read/Write Operations with Zero Latency ....... 14

Standby Mode ........................................................................ 14

Automatic Sleep Mode ........................................................... 15

RESET#: Hardware Reset Pin ............................................... 15

Output Disable Mode .............................................................. 15

Table 5. Am29DL640H Sector Architecture ....................................15

Table 6. Bank Address ....................................................................18

Table 7. SecSi

™ Sector Addresses ...............................................18

Sector/Sector Block Protection and Unprotection .................. 19

Table 8. Am29DL640H Boot Sector/Sector Block Addresses for

Protection/Unprotection ...................................................................19

Write Protect (WP#) ................................................................ 19

Table 9. WP#/ACC Modes ..............................................................20

Temporary Sector Unprotect .................................................. 20

Figure 1. Temporary Sector Unprotect Operation........................... 20

Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21

SecSi™ (Secured Silicon) Sector Flash Memory Region ...... 22

Figure 3. SecSi Sector Protect Verify.............................................. 23

Hardware Data Protection ...................................................... 23

Low V

CC Write Inhibit ........................................................... 23

Write Pulse “Glitch” Protection ............................................ 23

Logical Inhibit ...................................................................... 23

Power-Up Write Inhibit ......................................................... 23

Common Flash Memory Interface (CFI) . . . . . . . 23

Table 10. CFI Query Identification String ........................................ 24

System Interface String................................................................... 24

Table 12. Device Geometry Definition ............................................ 24

Table 13. Primary Vendor-Specific Extended Query ...................... 26

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 27

Reading Array Data ................................................................ 27

Reset Command ..................................................................... 27

Autoselect Command Sequence ............................................ 27

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence .............................................................. 27

Byte/Word Program Command Sequence ............................. 28

Unlock Bypass Command Sequence .................................. 28

Figure 4. Program Operation .......................................................... 29

Chip Erase Command Sequence ........................................... 29

Sector Erase Command Sequence ........................................ 29

Figure 5. Erase Operation.............................................................. 30

Erase Suspend/Erase Resume Commands ........................... 30

Table 14. Am29DL640H Command Definitions .............................. 31

Write Operation Status . . . . . . . . . . . . . . . . . . . . 32

DQ7: Data# Polling ................................................................. 32

Figure 6. Data# Polling Algorithm .................................................. 32

RY/BY#: Ready/Busy# ............................................................ 33

DQ6: Toggle Bit I .................................................................... 33

Figure 7. Toggle Bit Algorithm........................................................ 33

DQ2: Toggle Bit II ................................................................... 34

Reading Toggle Bits DQ6/DQ2 ............................................... 34

DQ5: Exceeded Timing Limits ................................................ 34

DQ3: Sector Erase Timer ....................................................... 34

Table 15. Write Operation Status ................................................... 35

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36

Figure 8. Maximum Negative Overshoot Waveform ...................... 36

Figure 9. Maximum Positive Overshoot Waveform........................ 36

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37

SRAM DC and Operating Characteristics . . . . . 38

Figure 10. I

CC1 Current vs. Time (Showing Active and

Automatic Sleep Currents) ............................................................. 39

Figure 11. Typical I

CC1 vs. Frequency ............................................ 39

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 12. Test Setup.................................................................... 40

Figure 13. Input Waveforms and Measurement Levels ................. 40

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41

SRAM CE#s Timing ................................................................ 41

Figure 14. Timing Diagram for Alternating Between

SRAM to Flash ............................................................................... 41

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42

Flash Read-Only Operations ................................................. 42

Figure 15. Read Operation Timings ............................................... 42

Hardware Reset (RESET#) .................................................... 43

Figure 16. Reset Timings ............................................................... 43

Word/Byte Configuration (CIOf) .............................................. 44

Figure 17. CIOf Timings for Read Operations................................ 44

Figure 18. CIOf Timings for Write Operations................................ 44

Erase and Program Operations .............................................. 45

Figure 19. Program Operation Timings.......................................... 46

Figure 20. Accelerated Program Timing Diagram .......................... 46

Figure 21. Chip/Sector Erase Operation Timings .......................... 47

Figure 22. Back-to-back Read/Write Cycle Timings ...................... 48

Figure 23. Data# Polling Timings (During Embedded Algorithms). 48

Figure 24. Toggle Bit Timings (During Embedded Algorithms)...... 49

Figure 25. DQ2 vs. DQ6................................................................. 49

Temporary Sector Unprotect .................................................. 50

Figure 26. Temporary Sector Unprotect Timing Diagram .............. 50

Figure 27. Sector/Sector Block Protect and

Unprotect Timing Diagram ............................................................. 51

Alternate CE#f Controlled Erase and Program Operations .... 52

Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program)

Operation Timings.......................................................................... 53

SRAM Read Cycle .................................................................. 54

Figure 29. SRAM Read Cycle—Address Controlled...................... 54

Figure 30. SRAM Read Cycle ........................................................ 55

SRAM Write Cycle .................................................................. 56

Figure 31. SRAM Write Cycle—WE# Control ................................ 56

类似零件编号 - AM41DL6408H8H70IS

制造商	部件名	数据表	功能描述
SPANSION	AM41DL6408G	1Mb / 63P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Advanced Micro Devices	AM41DL6408G	1Mb / 63P	64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
	AM41DL6408G25IS	1Mb / 63P	64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
	AM41DL6408G25IT	1Mb / 63P	64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
	AM41DL6408G30IS	1Mb / 63P	64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM

More results

类似说明 - AM41DL6408H8H70IS

制造商	部件名	数据表	功能描述
Advanced Micro Devices	DS42553	955Kb / 58P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
SPANSION	AM41DL3208G	1Mb / 65P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
SPANSION	AM42DL6404G	1,020Kb / 61P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Advanced Micro Devices	DS42515	830Kb / 57P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
	DS42585	958Kb / 58P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
	DS42587	958Kb / 58P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
	DS42514	832Kb / 57P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
	AM49DL640AG	1,005Kb / 65P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
SPANSION	AM42BDS640AG	1Mb / 72P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Advanced Micro Devices	DS42516	953Kb / 58P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

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