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EBE51RD8ABFA Datasheet(数据表) 16 Page - Elpida Memory

部件型号  EBE51RD8ABFA
说明  512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
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制造商  ELPIDA [Elpida Memory]
网页  http://www.elpida.com/en
标志 ELPIDA - Elpida Memory

EBE51RD8ABFA Datasheet(HTML) 16 Page - Elpida Memory

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EBE51RD8ABFA
Data Sheet E0402E40 (Ver. 4.0)
16
-5C
-4A
Frequency (Mbps)
533
400
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
Active bank A to active bank B
command period
tRRD
7.5
7.5
ns
Write recovery time
tWR
15
15
ns
Auto precharge write recovery +
precharge time
tDAL
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
tCK
1
Internal write to read command delay
tWTR
7.5
10
ns
Internal read to precharge command
delay
tRTP
7.5
7.5
ns
Exit self refresh to a non-read command tXSNR
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
200
tCK
Exit precharge power down to any non-
read command
tXP
2
2
tCK
Exit active power down to read
command
tXARD
2
2
tCK
3
Exit active power down to read
command
(slow exit/low power mode)
tXARDS 6
− AL
6
− AL
tCK
2, 3
CKE minimum pulse width (high and
low pulse width)
tCKE
3
3
tCK
Output impedance test driver delay
tOIT
0
12
0
12
ns
Auto refresh to active/auto refresh
command time
tRFC
105
105
ns
Average periodic refresh interval
tREFI
7.8
7.8
µs
Minimum time clocks remains ON after
CKE asynchronously drops low
tDELAY tIS + tCK + tIH
tIS + tCK + tIH
ns
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
DQS
/DQS
tDS
tDH
tDS
tDH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VREF
CK
/CK
tIS
tIH
tIS
tIH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VREF
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)




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