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EBE51RD8ABFA Datasheet(数据表) 15 Page - Elpida Memory

部件型号  EBE51RD8ABFA
说明  512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
下载  22 Pages
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制造商  ELPIDA [Elpida Memory]
网页  http://www.elpida.com/en
标志 ELPIDA - Elpida Memory

EBE51RD8ABFA Datasheet(HTML) 15 Page - Elpida Memory

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EBE51RD8ABFA
Data Sheet E0402E40 (Ver. 4.0)
15
AC Characteristics (TC = 0 to +85
°°°°C, VDD, VDDQ = 1.8V ± 0.1V, VSS = 0V)
(DDR2 SDRAM Component Specification)
-5C
-4A
Frequency (Mbps)
533
400
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
/CAS latency
CL
4
5
3
5
tCK
Active to read or write command delay
tRCD
15
15
ns
Precharge command period
tRP
15
15
ns
Active to active/auto refresh command
time
tRC
55
55
ns
DQ output access time from CK, /CK
tAC
−500
+500
−600
+600
ps
DQS output access time from CK, /CK
tDQSCK
−450
+450
−500
+500
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min.
(tCL, tCH)
min.
(tCL, tCH)
ps
Clock cycle time
tCK
3750
8000
5000
8000
ps
DQ and DM input hold time
tDH
225
275
ps
5
DQ and DM input setup time
tDS
100
150
ps
4
Control and Address input pulse width
for each input
tIPW
0.6
0.6
tCK
DQ and DM input pulse width for each
input
tDIPW
0.35
0.35
tCK
Data-out high-impedance time from
CK,/CK
tHZ
tAC max.
tAC max.
ps
Data-out low-impedance time from
CK,/CK
tLZ
tAC min.
tAC max.
tAC min.
tAC max.
ps
DQS-DQ skew for DQS and associated
DQ signals
tDQSQ
300
350
ps
DQ hold skew factor
tQHS
400
450
ps
DQ/DQS output hold time from DQS
tQH
tHP – tQHS
tHP – tQHS
ps
Write command to first DQS latching
transition
tDQSS
WL
− 0.25
WL + 0.25
WL
− 0.25
WL + 0.25
tCK
DQS input high pulse width
tDQSH
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
tCK
DQS falling edge to CK setup time
tDSS
0.2
0.2
tCK
DQS falling edge hold time from CK
tDSH
0.2
0.2
tCK
Mode register set command cycle time
tMRD
2
2
tCK
Write preamble setup time
tWPRES 0
0
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.25
0.25
tCK
Address and control input hold time
tIH
375
475
ps
5
Address and control input setup time
tIS
250
350
ps
4
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Active to precharge command
tRAS
40
70000
40
70000
ns
Active to auto-precharge delay
tRAP
tRCD min.
tRCD min.
ns




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