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EBE51RD8ABFA Datasheet(数据表) 11 Page - Elpida Memory

部件型号  EBE51RD8ABFA
说明  512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
下载  22 Pages
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制造商  ELPIDA [Elpida Memory]
网页  http://www.elpida.com/en
标志 ELPIDA - Elpida Memory

EBE51RD8ABFA Datasheet(HTML) 11 Page - Elpida Memory

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EBE51RD8ABFA
Data Sheet E0402E40 (Ver. 4.0)
11
DC Characteristics 1 (TC = 0 to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
Parameter
Symbol
Grade
max.
Unit
Test condition
Operating current
(ACT-PRE)
IDD0
-5C
-4A
1480
1310
mA
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating current
(ACT-READ-PRE)
IDD1
-5C
-4A
1680
1470
mA
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Precharge power-down
standby current
IDD2P
-5C
-4A
580
500
mA
all banks idle;
tCK = tCK (IDD);
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge quiet standby
current
IDD2Q
-5C
-4A
720
610
mA
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Idle standby current
IDD2N
-5C
-4A
760
660
mA
all banks idle;
tCK = tCK (IDD);CKE is H, /CS is H;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
IDD3P-F
-5C
-4A
850
750
mA
Fast PDN Exit
MRS(12) = 0
Active power-down
standby current
IDD3P-S
-5C
-4A
720
610
mA
all banks open;
tCK = tCK (IDD);
CKE is L;
Other control and
address bus inputs are
STABLE;
Data bus inputs are
FLOATING
Slow PDN Exit
MRS(12) = 1
Active standby current
IDD3N
-5C
-4A
1100
990
mA
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
Operating current
(Burst read operating)
IDD4R
-5C
-4A
2270
1830
mA
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Operating current
(Burst write operating)
IDD4W
-5C
-4A
2270
1830
mA
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING




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