数据搜索系统,热门电子元器件搜索
  Chinese▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

EBE51RD8ABFA Datasheet(数据表) 1 Page - Elpida Memory

部件型号  EBE51RD8ABFA
说明  512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
下载  22 Pages
Scroll/Zoom Zoom In 100% Zoom Out
制造商  ELPIDA [Elpida Memory]
网页  http://www.elpida.com/en
标志 ELPIDA - Elpida Memory

EBE51RD8ABFA Datasheet(HTML) 1 Page - Elpida Memory

  EBE51RD8ABFA 数据表 HTML 1Page - Elpida Memory EBE51RD8ABFA 数据表 HTML 2Page - Elpida Memory EBE51RD8ABFA 数据表 HTML 3Page - Elpida Memory EBE51RD8ABFA 数据表 HTML 4Page - Elpida Memory EBE51RD8ABFA 数据表 HTML 5Page - Elpida Memory EBE51RD8ABFA 数据表 HTML 6Page - Elpida Memory EBE51RD8ABFA 数据表 HTML 7Page - Elpida Memory EBE51RD8ABFA 数据表 HTML 8Page - Elpida Memory EBE51RD8ABFA 数据表 HTML 9Page - Elpida Memory Next Button
Zoom Inzoom in Zoom Outzoom out
 1 page
background image
Document No. E0402E40 (Ver. 4.0)
Date Published July 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2004
DATA SHEET
512MB Registered DDR2 SDRAM DIMM
EBE51RD8ABFA (64M words
×××× 72 bits, 1 Rank)
Description
The EBE51RD8ABFA is a 64M words
× 72 bits, 1 rank
DDR2 SDRAM Module, mounting 9 pieces of DDR2
SDRAM sealed in FBGA (
µBGA) package. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 4bits prefetch-pipelined architecture.
Data strobe (DQS and /DQS) both for read and write
are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
This module provides high density mounting without
utilizing
surface
mount
technology.
Decoupling
capacitors are mounted beside each FBGA (
µBGA) on
the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
• 240-pin socket type dual in line memory module
(DIMM)
 PCB height: 30.0mm
 Lead pitch: 1.0mm
 Lead-free
• 1.8V power supply
• Data rate: 533Mbps/400Mbps (max.)
• 1.8 V (SSTL_18 compatible) I/O
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, data strobe (DQS and /DQS) is
transmitted /received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Four internal banks for concurrent operation
(Component)
• Data mask (DM) for write data
• Burst length: 4, 8
• /CAS latency (CL): 3, 4, 5
• Auto precharge option for each burst access
• Auto refresh and self refresh modes
• 7.8µs average periodic refresh interval
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• 1 piece of PLL clock driver, 1 pieces of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)




HTML 页

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22 


数据表 下载

Go To PDF Page


链接网址


Privacy Policy
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ]  

关于 Alldatasheet    |   广告服务   |   联系我们   |   隐私政策   |   书签   |   链接交换   |   制造商名单
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl