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EBE51ED8AGFA Datasheet(数据表) 1 Page - Elpida Memory

部件型号  EBE51ED8AGFA
说明  512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
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制造商  ELPIDA [Elpida Memory]
网页  http://www.elpida.com/en
标志 ELPIDA - Elpida Memory

EBE51ED8AGFA Datasheet(HTML) 1 Page - Elpida Memory

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Document No. E0783E20 (Ver. 2.0)
Date Published October 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
DATA SHEET
512MB Unbuffered DDR2 SDRAM DIMM
EBE51ED8AGFA (64M words
× 72 bits, 1 Rank)
Description
The EBE51ED8AGFA is 64M words
× 72 bits, 1 rank
DDR2 SDRAM unbuffered module, mounting 9 pieces
of 512M bits DDR2 SDRAM sealed in FBGA (
µBGA)
package. Read and write operations are performed at
the cross points of the CK and the /CK.
This high-
speed data transfer is realized by the 4 bits prefetch-
pipelined architecture. Data strobe (DQS and /DQS)
both for read and write are available for high speed and
reliable data bus design.
By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable.
This module provides high
density
mounting
without
utilizing
surface
mount
technology.
Decoupling capacitors are mounted
beside each FBGA (
µBGA) on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
• 240-pin socket type dual in line memory module
(DIMM)
 PCB height: 30.0mm
 Lead pitch: 1.0mm
 Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 667Mbps/533Mbps/400Mbps (max.)
• SSTL_18 compatible I/O
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
(components)
• Data mask (DM) for write data
• Burst lengths: 4, 8
• /CAS Latency (CL): 3, 4, 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• Average refresh period
 7.8µs at 0°C ≤ TC ≤ +85°C
 3.9µs at +85°C < TC ≤ +95°C
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation




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