数据搜索系统,热门电子元器件搜索
  Chinese▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

EBE51ED8AEFA-6 Datasheet(数据表) 16 Page - Elpida Memory

部件型号  EBE51ED8AEFA-6
说明  512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
下载  22 Pages
Scroll/Zoom Zoom In 100% Zoom Out
制造商  ELPIDA [Elpida Memory]
网页  http://www.elpida.com/en
标志 ELPIDA - Elpida Memory

EBE51ED8AEFA-6 Datasheet(HTML) 16 Page - Elpida Memory

Back Button EBE51ED8AEFA-6 数据表 HTML 12Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 13Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 14Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 15Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 16Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 17Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 18Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 19Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 20Page - Elpida Memory Next Button
Zoom Inzoom in Zoom Outzoom out
 16 page
background image
EBE51ED8AEFA-6
Data Sheet E0724E10 (Ver. 1.0)
16
-6E
Frequency (Mbps)
667
Parameter
Symbol
min.
max.
Unit
Notes
Read preamble
tRPRE
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
tCK
Active to precharge command
tRAS
45
70000
ns
Active to auto-precharge delay
tRAP
tRCD min.
ns
Active bank A to active bank B command period
tRRD
7.5
ns
Write recovery time
tWR
15
ns
Auto precharge write recovery + precharge time
tDAL
(tWR/tCK)+
(tRP/tCK)
tCK
1
Internal write to read command delay
tWTR
7.5
ns
Internal read to precharge command delay
tRTP
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
tCK
Exit precharge power down to any non-read
command
tXP
2
tCK
Exit active power down to read command
tXARD
2
tCK
3
Exit active power down to read command
(slow exit/low power mode)
tXARDS
7
− AL
tCK
2, 3
CKE minimum pulse width (high and low pulse width) tCKE
3
tCK
Output impedance test driver delay
tOIT
0
12
ns
Auto refresh to active/auto refresh command time
tRFC
105
ns
Average periodic refresh interval
(0
°C ≤ TC ≤ +85°C)
tREFI
7.8
µs
(+85
°C < TC ≤ +95°C)
tREFI
3.9
µs
Minimum time clocks remains ON after CKE
asynchronously drops low
tDELAY
tIS + tCK + tIH
ns
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
DQS
/DQS
tDS
tDH
tDS
tDH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VREF
CK
/CK
tIS
tIH
tIS
tIH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VREF
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)




HTML 页

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22 


数据表 下载

Go To PDF Page


链接网址


Privacy Policy
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ]  

关于 Alldatasheet    |   广告服务   |   联系我们   |   隐私政策   |   书签   |   链接交换   |   制造商名单
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl