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EBE51ED8AEFA-6 Datasheet(数据表) 15 Page - Elpida Memory

部件型号  EBE51ED8AEFA-6
说明  512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
下载  22 Pages
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制造商  ELPIDA [Elpida Memory]
网页  http://www.elpida.com/en
标志 ELPIDA - Elpida Memory

EBE51ED8AEFA-6 Datasheet(HTML) 15 Page - Elpida Memory

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EBE51ED8AEFA-6
Data Sheet E0724E10 (Ver. 1.0)
15
Pin Capacitance (TA = 25°C, VDD = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
Symbol
Pins
min.
max.
Unit
Notes
Input capacitance
CI1
Address, /RAS, /CAS, /WE,
/CS, CKE, ODT
1.0
2.0
pF
1
Input capacitance
CI2
CK, /CK
1.0
2.0
pF
1
Data and DQS input/output
capacitance
CO
DQ, DQS, /DQS, DM, CB
2.5
3.5
pF
2
Notes: 1. Matching within 0.25pF.
2. Matching within 0.50pF.
AC Characteristics (TC = 0°C to +85
°C, VDD, VDDQ = 1.8V ± 0.1V, VSS = 0V)
(DDR2 SDRAM Component Specification)
-6E
Frequency (Mbps)
667
Parameter
Symbol
min.
max.
Unit
Notes
/CAS latency
CL
5
5
tCK
Active to read or write command delay
tRCD
15
ns
Precharge command period
tRP
15
ns
Active to active/auto refresh command time
tRC
60
ns
DQ output access time from CK, /CK
tAC
−450
+450
ps
DQS output access time from CK, /CK
tDQSCK
−400
+400
ps
CK high-level width
tCH
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
tCK
CK half period
tHP
min.
(tCL, tCH)
ps
Clock cycle time
tCK
3000
8000
ps
DQ and DM input hold time
tDH
175
ps
5
DQ and DM input setup time
tDS
100
ps
4
Control and Address input pulse width for each input tIPW
0.6
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
tCK
Data-out high-impedance time from CK,/CK
tHZ
tAC max.
ps
Data-out low-impedance time from CK,/CK
tLZ
tAC min.
tAC max.
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
240
ps
DQ hold skew factor
tQHS
340
ps
DQ/DQS output hold time from DQS
tQH
tHP – tQHS
ps
Write command to first DQS latching transition
tDQSS
WL
− 0.25
WL + 0.25
tCK
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS falling edge to CK setup time
tDSS
0.2
tCK
DQS falling edge hold time from CK
tDSH
0.2
tCK
Mode register set command cycle time
tMRD
2
tCK
Write postamble
tWPST
0.4
0.6
tCK
Write preamble
tWPRE
0.35
tCK
Address and control input hold time
tIH
275
ps
5
Address and control input setup time
tIS
200
ps
4




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